Optimizing Reduced Voltage Tests for Faster Results
Recent research by P. Venkataramani and V. D. Agrawal focuses on the implications of reducing supply voltage during testing. The critical path slows down, power consumption decreases, and the test clock runs slower due to power constraints. By analyzing the effects of reducing voltage on power and frequency, researchers have identified strategies to optimize test performance and reduce test time significantly. This work, supported by an NSF grant, showcases how careful selection of supply voltage can lead to more efficient testing processes, ensuring that test activities do not exceed designed power limits.
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Presentation Transcript
Reduced Voltage Test Can be Faster! Vishwani D. Agrawal vagrawal@eng.auburn.edu Support from NSF Grant 1116213 11/7/2012 ITC '12: Elevator Talk 1
Effects of Reducing Supply Voltage Critical path slows down. Power reduces as V2. Test produces more than functional activity; consumes more power that the circuit is designed for. Test clock is slower due to power constrain. 11/7/2012 ITC '12: Elevator Talk 2
Power and Frequency vs. Voltage Structure constrained test Power constrained test Peak power/cycle during test (structure constrained) Max. clock frequency PMAXfunc Vtest Nominal voltage Voltage VDD 11/7/2012 ITC '12: Elevator Talk 3
Reduced Voltage Test Results PMAX per cycle (mW) (MHz) 1.8V test freq. Test clock freq. (MHz) Circuit (180nm CMOS) Test voltage (volts) Test time reduction (%) s298 1.2 187 1.08 500 62.5 s13207 21.3 110 1.45 165 40.3 s38584 110.6 129 1.50 187 31.0 P. Venkataramani and V. D. Agrawal, Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage, Proc. 26th International Conf. VLSI Design, January 2013. 11/7/2012 ITC '12: Elevator Talk 4
