Memory Testing Methodology Overview
Memory testing methodologies for embedded memory involve fault characteristics like Address Decoder Fault, Stuck-At Fault, Transition Fault, and Coupling Fault. Traditional solutions include Walking Pattern-Complexity, Sliding Pattern-Complexity, and Butterfly Pattern-Complexity. Embedded memories have unique characteristics where address, data, and control signals are not directly accessible through I/O pins. Solutions like March Test and Memory Built-In-Self Test provide a structured approach to testing memory and detecting faults.
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Presentation Transcript
MEMORY TESTING METHODOLOGIES For embedded memory Minghuan Zhao 1
Fault Characteristics Address-Decoder Fault (AF) Stuck-At Fault (SAF) Transition Fault (TF) Coupling Fault (CF) 3
Traditional solution Walking Pattern-Complexity 2N2 Sliding Pattern-Complexity 4N1.5 Butterfly Pattern-Complexity 5NlogN Means Size 1G N 10.5sec NlogN 5.3min N1.5 4days N2 366years 4
Embedded memory Characteristics embedded memory s address, data, and control signals are usually not directly accessible through the I/O pins. 5
Solution: March && Memory Built-In-Self Test March Test typically has complexity: O(N) Linear access to memory by a specific order Memory Built-In-Self Test(Architecture) Normal data in Model select Data generator Self-test controller Test clk reset Address Generator RAM Normal address Normal data out Reference Data receiver (Comparator) 6
March C-(evolved March C) March C- is a classical algorithm which is the foundation of other algorithms { (w0); (r0,w1); (r1,w0); (r0,w1); (r1,w0); (r0)} Complexity 5N=>O(N) ascending order descending order r0:read 0 w1:write 1 March Element (w0): M0 7
{(w0);(r0,w1);(r1,w0);(r0,w1); (r1,w0); (r0)} M0 M1 M2 M3 M4 M5 Address Fault, Transition Fault: M2 and M3 M1 0 1 0 1 0 1 1 0 M2 1 0 1 0 Stuck-At Fault: overwrite 0 s and 1 s M2 1 0 1 0 1 0 8
{(w0);(r0,w1);(r1,w0);(r0,w1); (r1,w0); (r0)} M0 M1 M2 M3 M4 M5 Coupling Fault (CF) j< i, Cj affected by Ci M1: Ci 1->0 falling behavior affect Cj M2: Ci 0->1 raising behavior affect Cj M1 1 0 1 0 1 M2 0 1 0 1 0 0(j) 1 2(i) j> i, detected by M3 and M4 9
Other March algorithm SAF ALL ALL ALL ALL ALL ALL ALL AF Some ALL ALL ALL ALL ALL ALL TF CF MATS MATS++ March X March C- March A March B March Y ALL ALL ALL ALL ALL Some ALL Some Some Some 10
Challenge Silicon area overhead Complexity can be less than O(N) Faults coverage Decrease test instructions and data Normal data in Model select Data generator Self-test controller Test clk reset Address Generato r RAM Normal address Normal out data Reference Data receiver (Comparator) 11