Makefiles in Software Development
What do I need for today?
•
Log into compute
•
Download files from Lab on Blackboard
CSCE-221
Makefile Part2 (Advanced)
Emil Thomas
03/21/19
Based on slides by Prof. Jeremy Gibson(UMBC) and Prof. Shawn Lupoli (TAMU)
3
Makefile Review
foobar.o: foobar.cpp foobar.h
g++ -std=c++11 -Wall -c foobar.cpp
T
a
r
g
e
t
The file to create. In this
case an object file: foobar.o
D
e
p
e
n
d
e
n
c
y
L
i
s
t
The files that are required to
create the object file. In this
case foobar.cpp and foobar.h
<
T
A
B
>
Used to
signal what
follows as
an action
A
c
t
i
o
n
(
s
)
What needs to be done to create the
target. In this case it is the separate
compilation of foobar.cpp
4
Makefile Macros
•
Similar to a
#define
or alias – use when you need
the same thing over and over
•
Syntax to define macro is:
•
MACRO_NAME = content to be substituted for MACRO_NAME
•
Benefits: easy to make changes – simply change in 1 place
rather than on all targets, etc…
PROJ = Driver.out
CXX = g++
CXXFLAGS = -g -ansi –Wall –std=c++11
OBJS = Driver.o Inventory.o Cd.o Date.o
5
Makefile Macros
•
To access a declared macro simply put the name of the macro inside
parenthesis after a dollar sign
•
Syntax to recall macro:
•
$(MACRO_NAME)
$(PROJ): $(OBJS)
$(CXX) $(CXXFLAGS) -o $(PROJ) $(OBJS)
Driver.o: Driver.cpp
$(CXX) $(CXXFLAGS) -c Driver.cpp
Date.o
: Date.cpp Date.h
$(CXX) $(CXXFLAGS) -c Date.cpp
Makefile using Command line arguments
•
Use a macro name inside Makefile
•
The value of this macro must be provided through command line
•
Command line
make run FILE=”testfilenames.txt”
•
Inside Makefile
run:
./$(PROJ) $FILE
Makefile Special Macros
•
The Macro
@
evaluates to the name of the current target
$(PROJ)
: $(OBJS)
$(CXX) -o
$@
$(OBJS)
Is equivalent to
Driver.out
:
Driver.o Inventory.o Cd.o Date.o
g++ -o
Driver.out
Driver.o Inventory.o Cd.o Date.o
Makefile Special Macros
•
The Macro
<
evaluates to the first item in the dependency list
Driver.o:
Driver.cpp
Inventory.h
$(CXX) $(CXXFLAGS) -c
$<
Means
Driver.o:
Driver.cpp
Inventory.h
$(CXX) $(CXXFLAGS) -c
Driver.cpp
Makefile Pattern Substitution
•
A pattern rule looks like an ordinary rule, except that its target
contains the character ‘%’ (exactly one of them).
•
The target is considered a pattern for matching file names;
•
‘%.o
:
%.cpp’ says how to make any file
stem
.o from
stem
.cpp
•
Eg.
%.o : %.cpp
$(CXX) $(CXXFLAGS) -c $<
Demonstration in Compute
Combining Pattern rule & Macros
11
Phony Targets
•
You can specify targets that do auxiliary tasks and do not actually
compile code
•
Remove object and executable files
•
Print source code
•
Submit all code to git hub account
•
These tasks do not require looking at the timestamps on files and
thus it is good practice to let make know that there is no “real” target
for a rule, and that it should just execute the action list
12
Phony Targets
•
The syntax is just like any other rule except the rule is
proceeded by a .PHONY declaration
•
Syntax is: .PHONY: target
•
Comes handy to run valgrind, to make a zip, add files
to your git hub account, etc…
.PHONY: clean finish
clean:
rm –rf *.o
rm –rf driver.out
finish:clean
rm –rf ./Proj3.zip
zip Proj3.zip ./*
Exercise to be submitted to ecampus
•
Login to
compute.cs.tamu.edu
using your netid and password
•
Go to your csce221 folder and make a subfolder lab9_makefile
•
cd csce221
•
mkdir lab9_makefile
•
cd lab9_makefile
•
Retrieve the files using
•
(after the first one below, just hit up arrow and edit the filename at the end)
•
wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/Makefile.txt
•
wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/driver.cpp
•
wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/LinkedList.cpp
•
wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/LinkedList.h
•
Exercise instructions are ON the makefile given
Submit the Survey under ecampus->lab1_makefile
Questions?
Explore the fundamentals of Makefiles for efficient software development, including defining macros, dependencies, targets, and special macros. Learn how to use command line arguments and access declared macros to streamline the build process. Enhance your knowledge with valuable insights and practical examples from industry experts.
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What do I need for today? Log into compute Download files from Lab on Blackboard
CSCE-221 Makefile Part2 (Advanced) Emil Thomas 03/21/19 Based on slides by Prof. Jeremy Gibson(UMBC) and Prof. Shawn Lupoli (TAMU)
Makefile Review Dependency List The files that are required to create the object file. In this case foobar.cpp and foobar.h Target The file to create. In this case an object file: foobar.o foobar.o: foobar.cpp foobar.h g++ -std=c++11 -Wall -c foobar.cpp <TAB> Used to signal what follows as an action Action(s) What needs to be done to create the target. In this case it is the separate compilation of foobar.cpp 3
Makefile Macros Similar to a #define or alias use when you need the same thing over and over Syntax to define macro is: MACRO_NAME = content to be substituted for MACRO_NAME Benefits: easy to make changes simply change in 1 place rather than on all targets, etc PROJ = Driver.out CXX = g++ CXXFLAGS = -g -ansi Wall std=c++11 OBJS = Driver.o Inventory.o Cd.o Date.o 4
Makefile Macros To access a declared macro simply put the name of the macro inside parenthesis after a dollar sign Syntax to recall macro: $(MACRO_NAME) $(PROJ): $(OBJS) $(CXX) $(CXXFLAGS) -o $(PROJ) $(OBJS) Driver.o: Driver.cpp $(CXX) $(CXXFLAGS) -c Driver.cpp Date.o : Date.cpp Date.h $(CXX) $(CXXFLAGS) -c Date.cpp 5
Makefile using Command line arguments Use a macro name inside Makefile The value of this macro must be provided through command line Command line make run FILE= testfilenames.txt Inside Makefile run: ./$(PROJ) $FILE
Makefile Special Macros The Macro @ evaluates to the name of the current target $(PROJ): $(OBJS) $(CXX) -o $@ $(OBJS) Is equivalent to Driver.out: Driver.o Inventory.o Cd.o Date.o g++ -o Driver.out Driver.o Inventory.o Cd.o Date.o
Makefile Special Macros The Macro < evaluates to the first item in the dependency list Driver.o: Driver.cpp Inventory.h $(CXX) $(CXXFLAGS) -c $< Means Driver.o: Driver.cpp Inventory.h $(CXX) $(CXXFLAGS) -c Driver.cpp
Makefile Pattern Substitution A pattern rule looks like an ordinary rule, except that its target contains the character % (exactly one of them). The target is considered a pattern for matching file names; %.o : %.cpp says how to make any file stem.o from stem.cpp Eg. %.o : %.cpp $(CXX) $(CXXFLAGS) -c $<
Demonstration in Compute Combining Pattern rule & Macros
Phony Targets You can specify targets that do auxiliary tasks and do not actually compile code Remove object and executable files Print source code Submit all code to git hub account These tasks do not require looking at the timestamps on files and thus it is good practice to let make know that there is no real target for a rule, and that it should just execute the action list 11
Phony Targets The syntax is just like any other rule except the rule is proceeded by a .PHONY declaration Syntax is: .PHONY: target Comes handy to run valgrind, to make a zip, add files to your git hub account, etc .PHONY: clean finish clean: rm rf *.o rm rf driver.out finish:clean rm rf ./Proj3.zip zip Proj3.zip ./* 12
Exercise to be submitted to ecampus Login to compute.cs.tamu.edu using your netid and password Go to your csce221 folder and make a subfolder lab9_makefile cd csce221 mkdir lab9_makefile cd lab9_makefile Retrieve the files using (after the first one below, just hit up arrow and edit the filename at the end) wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/Makefile.txt wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/driver.cpp wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/LinkedList.cpp wget http://faculty.cse.tamu.edu/slupoli/notes/DataStructures/labs/code/makepart2/LinkedList.h Exercise instructions are ON the makefile given
