Enhancing Out-of-Order Completion with In-Order Retirement
To improve performance, instructions are retired in dispatch order rather than completion order. Introduce appearance changes in architectural state, track oldest and newest instructions, and allow rollback to un-retired instructions. Implement reorder buffers, separate rename registers, and utilize Tomasulo's method for support. Architectural registers hold non-completed values, with a distinct architecture for in-order execution. Handle retrieval from registers that haven't committed to architectural state.
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(c) Derek Chiou & Mattan Erez 1 Out-of-Order Completion => In-Order Retirement What do we need to do? Provide appearance that instructions write-back (retire) to architectural state in dispatch order Real registers Memory Must provide way to use non-retired state Tomasulo already supports that But, does Tomasulo allow us to uncomplete a completed instruction? Need two things Track what is oldest instruction and newest write to a reg Provide ability to rollback to a specific un-retired instruction 1
(c) Derek Chiou & Mattan Erez 2 Determining Order Reorder Buffer == Completion Buffer Reorder buffer tracks all outstanding instructions in issue order Determines when instruction becomes oldest Retires oldest instruction(s) by copying pending value to architectural register file If need to rollback to oldest instruction, throw away Bread crumbs to determine state of each instruction Similar to scoreboard 2
(c) Derek Chiou & Mattan Erez 3 In-Order Execution => In-Order State Update One possible strategy Architectural registers Consistent with in-order execution AND separate rename registers Hold non-completed values Value value 10 11 12 13 15 18 25 valid A B C D E F G F T F F F F F Tag committed R0 R1 R2 R3 0 1 2 3 T T F F B A What registers are architectural registers? Can R3 s value be read? If so, what is it? Can R0 s value be read? If so, what is it? Can R2 s value be read? If so, what is it? How many rename registers required? RAT 3
(c) Derek Chiou & Mattan Erez 4 Possible Reorder Buffer Rename Reg Valid Issued Done Inst address Arch Reg head 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0x0100 0x0200 0x0204 --- --- B A R3 R5 tail When can an instruction retire? What do you do? How do you read a register that hasn t committed to arch state? 4
(c) Derek Chiou & Mattan Erez 5 Possible Reorder Buffer Actual Physical Valid Issued Done Inst address Arch Reg head 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0x0100 0x0200 0x0204 --- --- R3 Value Value R5 tail When can an instruction retire? What do you do? How do you read a register that hasn t committed to arch state? 5
