Debugging PMP Systems: A Guideline for Application Engineers

 
H
o
w
 
t
o
 
d
e
b
u
g
 
P
M
P
 
s
y
s
t
e
m
s
A
 
g
u
i
d
e
l
i
n
e
 
f
o
r
 
A
p
p
l
i
c
a
t
i
o
n
 
E
n
g
i
n
e
e
r
s
 
V
i
n
c
e
n
z
o
 
P
i
z
z
o
l
a
n
t
e
N
o
v
e
m
b
e
r
 
2
0
1
3
 
 
A
g
e
n
d
a
 
S
e
c
t
i
o
n
 
I
 
 
T
h
e
 
p
a
t
h
 
o
f
 
t
h
e
 
a
n
a
l
y
s
i
s
 
S
e
c
t
i
o
n
 
I
I
 
 
T
h
e
 
t
e
c
h
n
i
c
a
l
 
a
s
p
e
c
t
s
 
S
e
c
t
i
o
n
 
I
I
I
 
 
W
h
e
n
 
g
u
i
l
t
y
 
i
s
 
t
h
e
 
l
a
y
o
u
t
 
TI Information – Selective Disclosure
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
T
r
a
c
e
 
I
n
d
u
c
t
a
n
c
e
 
T
y
p
i
c
a
l
1
0
m
i
l
s
t
r
a
c
e
 
C
a
s
e
 
S
t
u
d
y
:
 
I
d
e
a
l
 
W
o
r
l
d
c
u
r
r
e
n
t
 
s
o
u
r
c
e
V
c
I
s
 
C
a
s
e
 
S
t
u
d
y
:
 
 
N
o
n
 
I
d
e
a
l
 
W
o
r
l
d
c
u
r
r
e
n
t
 
s
o
u
r
c
e
V
c
I
s
 
s
t
r
a
y
 
i
n
d
u
c
t
a
n
c
e
 
(
P
C
B
 
t
r
a
c
e
s
)
 
C
a
s
e
 
S
t
u
d
y
:
 
 
N
o
n
 
I
d
e
a
l
 
W
o
r
l
d
c
u
r
r
e
n
t
 
s
o
u
r
c
e
V
c
I
s
 
H
i
g
h
 
d
i
/
d
t
 
V
c
g
 
H
i
g
h
 
d
i
/
d
t
 
c
a
u
s
e
s
 
n
o
i
s
e
a
c
c
r
o
s
s
 
s
t
r
a
y
 
i
n
d
u
c
t
a
n
c
e
!
 
 
A
l
l
 
e
l
e
m
e
n
t
s
,
 
i
n
c
l
u
d
i
n
g
P
C
B
 
t
r
a
c
e
s
,
 
h
a
v
e
 
p
a
r
a
s
i
t
i
c
L
,
 
R
,
 
C
H
i
g
h
 
d
i
/
d
t
 
t
h
r
u
 
p
a
r
a
s
i
t
i
c
 
L
p
r
o
d
u
c
e
s
 
v
o
l
t
a
g
e
 
s
p
i
k
e
s
M
u
s
t
 
a
v
o
i
d
 
i
n
j
e
c
t
i
n
g
 
t
h
e
s
e
c
u
r
r
e
n
t
s
 
i
n
t
o
 
t
h
e
 
g
r
o
u
n
d
p
l
a
n
e
 
 
F
i
r
s
t
,
 
i
d
e
n
t
i
f
y
 
h
i
g
h
 
d
i
/
d
t
 
p
a
t
h
s
I
m
p
a
c
t
 
o
f
 
H
i
g
h
 
d
i
/
d
t
 
H
o
w
 
t
o
 
D
e
a
l
 
w
i
t
h
 
t
h
e
 
N
o
i
s
e
 
G
e
n
e
r
a
t
o
r
s
 
N
o
t
e
 
t
h
e
 
r
e
-
r
o
u
t
e
 
o
f
 
t
h
e
d
i
o
d
e
-
r
e
t
u
r
n
 
p
a
t
h
F
o
r
c
e
s
 
p
u
l
s
e
c
u
r
r
e
n
t
s
 
d
i
r
e
c
t
l
y
b
a
c
k
 
t
o
 
i
n
p
u
t
 
c
a
p
K
e
e
p
s
 
h
i
g
h
 
d
i
/
d
t
c
u
r
r
e
n
t
s
 
o
u
t
 
o
f
g
r
o
u
n
d
D
i
o
d
e
 
a
n
o
d
e
 
m
a
y
a
c
t
u
a
l
l
y
 
b
e
 
a
 
b
i
t
n
o
i
s
i
e
r
,
 
b
u
t
 
w
h
o
c
a
r
e
s
?
C
a
n
 
a
p
p
l
y
 
t
h
e
 
s
a
m
e
r
a
t
i
o
n
a
l
e
 
t
o
 
a
l
l
t
o
p
o
l
o
g
i
e
s
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
L
o
c
a
t
i
n
g
 
t
h
e
 
h
i
g
h
 
d
i
/
d
t
 
p
a
t
h
s
 
B
u
c
k
 
B
o
o
s
t
 
S
e
p
i
c
 
B
u
c
k
:
 
H
i
g
h
 
d
i
/
d
t
 
P
a
t
h
s
 
Draw the switch-ON current path in one color
Then draw the switch-OFF path in another
Any part of the circuit that has only a single color, or both with current
arrows in opposite direction, is a high di/dt path
W
o
r
k
s
 
f
o
r
 
a
l
l
 
t
o
p
o
l
o
g
i
e
s
!
 
H
i
g
h
d
i
/
d
t
 
 
B
u
c
k
:
 
H
i
g
h
 
d
i
/
d
t
 
P
a
t
h
s
 
I
d
e
n
t
i
f
i
e
d
 
#
1
 
M
o
s
t
 
i
m
p
o
r
t
a
n
t
 
p
a
t
h
s
!
 
K
e
e
p
 
t
h
i
s
 
G
N
D
 
p
a
t
h
 
s
e
p
a
r
a
t
e
d
 
f
r
o
m
 
t
h
e
G
N
D
 
p
l
a
n
e
!
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
 
E
x
a
m
p
l
e
 
w
i
t
h
 
L
a
b
 
R
e
s
u
l
t
s
 
 
T
h
i
s
 
i
s
 
t
h
e
 
s
c
h
e
m
a
t
i
c
 
o
f
 
a
n
 
a
c
t
u
a
l
 
L
M
3
1
0
0
 
d
e
m
o
 
b
o
a
r
d
 
 
2
5
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
1
0
0
m
V
/
d
i
v
 
2
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
1
0
0
m
V
/
d
i
v
V
O
 
(
A
C
)
 
W
i
t
h
 
I
m
p
r
o
p
e
r
 
L
a
y
o
u
t
 
LM3100 Rev. B -
Problem layout:
B
o
t
t
o
m
 
c
o
p
p
e
r
T
o
p
 
S
i
l
k
T
o
p
 
c
o
p
p
e
r
I
m
p
r
o
p
e
r
 
L
a
y
o
u
t
 
A
r
t
w
o
r
k
 
 
R
e
c
a
l
l
 
B
u
c
k
 
d
i
/
d
t
 
P
a
t
h
s
 
#
1
 
M
o
s
t
 
i
m
p
o
r
t
a
n
t
 
p
a
t
h
s
!
 
K
e
e
p
 
t
h
i
s
 
G
N
D
 
p
a
t
h
 
s
e
p
a
r
a
t
e
d
 
f
r
o
m
 
t
h
e
G
N
D
 
p
l
a
n
e
!
 
I
m
p
r
o
p
e
r
 
L
a
y
o
u
t
 
A
r
t
w
o
r
k
 
-
 
T
h
e
 
C
r
i
t
i
c
a
l
 
P
a
t
h
s
 
-
R
e
d
 
=
 
B
o
t
t
o
m
B
l
u
e
 
=
 
T
o
p
 
I
m
p
r
o
v
e
d
 
L
a
y
o
u
t
 
A
r
t
w
o
r
k
LM3100 Rev. C -
Proper layout:
B
o
t
t
o
m
 
c
o
p
p
e
r
T
o
p
 
S
i
l
k
T
o
p
 
c
o
p
p
e
r
 
 
I
m
p
r
o
p
e
r
 
L
a
y
o
u
t
 
A
r
t
w
o
r
k
 
-
 
T
h
e
 
C
r
i
t
i
c
a
l
 
P
a
t
h
s
 
-
R
e
d
 
=
 
B
o
t
t
o
m
B
l
u
e
 
=
 
T
o
p
 
 
2
5
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
1
0
0
m
V
/
d
i
v
 
2
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
1
0
0
m
V
/
d
i
v
 
V
O
 
(
A
C
)
 
W
i
t
h
 
I
m
p
r
o
p
e
r
 
L
a
y
o
u
t
 
(
R
e
v
.
 
B
)
 
 
2
5
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
2
0
m
V
/
d
i
v
 
2
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
2
0
m
V
/
d
i
v
 
V
O
 
(
A
C
)
 
I
m
p
r
o
v
e
d
 
L
a
y
o
u
t
 
(
R
e
v
.
 
C
)
 
 
2
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
1
0
0
m
V
/
d
i
v
 
(
R
e
v
.
 
B
)
 
2
0
M
H
z
 
B
a
n
d
w
i
d
t
h
,
2
0
m
V
/
d
i
v
 
(
R
e
v
.
 
C
)
 
I
m
p
r
o
v
e
d
 
L
a
y
o
u
t
 
E
f
f
e
c
t
s
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
4
-
L
a
y
e
r
s
 
P
C
B
 
U
n
d
e
s
i
r
e
d
 
Layer 1 – Power components
Layer 2 – Small signal
Layer 3 – GND plane
Layer 4 – Small signal / controller
 
Switching currents from power
components to GND plane cause
capacitive cross-talk to the small
signal
 
D
e
s
i
r
e
d
 
Layer 1 – Power components
Layer 2 – GND plane
L
a
y
e
r
 
3
 
 
S
m
a
l
l
 
s
i
g
n
a
l
Layer 4 – Small signal / controller
 
GND plane separate the small
signal and forms a mechanical
bulk cap with the Power layer
TI Information – Selective Disclosure
 
6
-
L
a
y
e
r
s
 
P
C
B
 
U
n
d
e
s
i
r
e
d
 
Layer 1 – Power components
Layer 2 – Small signal
Layer 3 – GND plane
Layer 4 – DC power / GND plane
Layer 5 – Small signal
Layer 6 – Power components /
controller
 
D
e
s
i
r
e
d
 
Layer 1 – Power components
Layer 2 – GND plane
L
a
y
e
r
 
3
 
 
S
m
a
l
l
 
s
i
g
n
a
l
Layer 4 – Small signal
Layer 5 – DC power / GND plane
Layer 6 – Power components /
controller
TI Information – Selective Disclosure
 
DC power and GND planes work as reference planes in AC
In a multilayers PCB the GND plane should not be fragmented
 
 
L
a
y
o
u
t
 
g
u
i
d
e
l
i
n
e
s
 
f
o
r
 
t
h
e
 
P
o
w
e
r
 
M
a
n
a
g
e
m
e
n
t
 
The origins of the noise
 
Reccomended layout per topology
 
Real life example
 
Reccomended layers stack-up
 
Land patterns of power components
 
TI Information – Selective Disclosure
 
 
L
a
n
d
 
p
a
t
t
e
r
n
s
 
o
f
 
p
o
w
e
r
 
c
o
m
p
o
n
e
n
t
s
 
TI Information – Selective Disclosure
 
 
C
o
n
n
e
c
t
i
n
g
 
B
y
p
a
s
s
 
C
a
p
a
c
i
t
o
r
s
 
C
o
n
n
e
c
t
i
n
g
 
t
o
 
h
i
g
h
 
f
r
e
q
u
e
n
c
y
 
b
y
p
a
s
s
 
c
a
p
s
:
T
h
i
s
 
a
s
s
u
m
e
s
 
a
 
c
o
n
n
e
c
t
i
o
n
 
i
n
t
o
 
i
n
t
e
r
n
a
l
 
p
l
a
n
e
s
 
 
 
 
 
L
o
n
g
 
t
h
i
n
 
t
r
a
c
e
s
 
a
d
d
i
n
d
u
c
t
a
n
c
e
 
a
n
d
 
e
f
f
e
c
t
i
v
e
l
y
i
s
o
l
a
t
e
 
t
h
e
 
c
a
p
a
c
i
t
o
r
K
e
e
p
i
n
g
 
v
i
a
s
 
c
l
o
s
e
 
t
o
 
p
a
d
s
m
i
n
i
m
i
z
e
s
 
p
a
r
a
s
i
t
i
c
i
n
d
u
c
t
a
n
c
e
D
o
u
b
l
e
d
 
v
i
a
s
 
f
u
r
t
h
e
r
 
r
e
d
u
c
e
i
n
d
u
c
t
a
n
c
e
T
h
i
s
 
t
e
c
h
n
i
q
u
e
 
f
u
r
t
h
e
r
 
r
e
d
u
c
e
s
i
n
d
u
c
t
a
n
c
e
 
b
y
 
r
e
d
u
c
i
n
g
 
t
h
e
h
i
g
h
 
f
r
e
q
u
e
n
c
y
 
l
o
o
p
 
a
r
e
a
 
 
T
e
r
r
i
b
l
e
!
 
G
o
o
d
 
B
e
t
t
e
r
 
B
e
s
t
 
S
u
p
e
r
!
 
 
T
E
R
R
I
B
L
E
 
G
O
O
D
 
C
o
n
n
e
c
t
i
n
g
 
B
y
p
a
s
s
 
C
a
p
a
c
i
t
o
r
s
T
h
a
n
k
 
Y
o
u
!
 
Q
u
e
s
t
i
o
n
s
?
Slide Note
Embed
Share

Comprehensive guideline by Vincenzo Pizzolante on debugging PMP systems for application engineers, covering topics like analysis, technical aspects, layout guidelines, trace inductance, case studies, and dealing with noise generators. Includes real-life examples and actionable solutions for managing power management layouts effectively.

  • Debugging
  • PMP Systems
  • Application Engineers
  • Layout Guidelines
  • Noise Generators

Uploaded on Oct 05, 2024 | 1 Views


Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

E N D

Presentation Transcript


  1. How to debug PMP systems A guideline for Application Engineers Vincenzo Pizzolante November 2013 TI Information Selective Disclosure TI Information Selective Disclosure

  2. Agenda Section I The path of the analysis Section II The technical aspects Section III When guilty is the layout TI Information Selective Disclosure

  3. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  4. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  5. Trace Inductance Typical 10mils trace

  6. Case Study: Ideal World Is Is current source Vc Vc

  7. Case Study: Non Ideal World stray inductance (PCB traces) Is Is current source Vc Vc

  8. Case Study: Non Ideal World High di/dt Is Is current source Vc Vcg Vcg Vc High di/dt causes noise accross stray inductance! High EMI

  9. Impact of High di/dt VIN All elements, including PCB traces, have parasitic L, R, C High di/dt thru parasitic L produces voltage spikes Vout Must avoid injecting these currents into the ground plane First, identify high di/dt paths

  10. How to Deal with the Noise Generators VIN Note the re-route of the diode-return path Forces pulse currents directly back to input cap Keeps high di/dt currents out of ground Diode anode may actually be a bit noisier, but who cares? Can apply the same rationale to all topologies Vout

  11. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  12. Locating the high di/dt paths Buck Boost Sepic

  13. Buck: High di/dt Paths Draw the switch-ON current path in one color Then draw the switch-OFF path in another Any part of the circuit that has only a single color, or both with current arrows in opposite direction, is a high di/dt path Works for all topologies! High di/dt

  14. Buck: High di/dt Paths Identified #1 Most important paths! Keep this GND path separated from the GND plane!

  15. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  16. Example with Lab Results This is the schematic of an actual LM3100 demo board

  17. VO (AC) With Improper Layout 250MHz Bandwidth, 100mV/div 20MHz Bandwidth, 100mV/div

  18. Improper Layout Artwork LM3100 Rev. B - Problem layout: Top Silk Bottom copper Top copper

  19. Recall Buck di/dt Paths #1 Most important paths! Keep this GND path separated from the GND plane!

  20. Improper Layout Artwork - The Critical Paths - Red = Bottom Blue = Top

  21. Improved Layout Artwork LM3100 Rev. C - Proper layout: Top Silk Top copper Bottom copper

  22. Improper Layout Artwork - The Critical Paths - Red = Bottom Blue = Top

  23. VO (AC) With Improper Layout (Rev. B) 250MHz Bandwidth, 100mV/div 20MHz Bandwidth, 100mV/div

  24. VO (AC) Improved Layout (Rev. C) 250MHz Bandwidth, 20mV/div 20MHz Bandwidth, 20mV/div

  25. Improved Layout Effects 20MHz Bandwidth, 100mV/div (Rev. B) 20MHz Bandwidth, 20mV/div (Rev. C)

  26. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  27. 4-Layers PCB Desired Undesired Layer 1 Power components Layer 2 GND plane Layer 3 Small signal Layer 4 Small signal / controller Layer 1 Power components Layer 2 Small signal Layer 3 GND plane Layer 4 Small signal / controller GND plane separate the small signal and forms a mechanical bulk cap with the Power layer Switching currents from power components to GND plane cause capacitive cross-talk to the small signal TI Information Selective Disclosure

  28. 6-Layers PCB Desired Undesired Layer 1 Power components Layer 2 GND plane Layer 3 Small signal Layer 4 Small signal Layer 5 DC power / GND plane Layer 6 Power components / controller Layer 1 Power components Layer 2 Small signal Layer 3 GND plane Layer 4 DC power / GND plane Layer 5 Small signal Layer 6 Power components / controller DC power and GND planes work as reference planes in AC In a multilayers PCB the GND plane should not be fragmented TI Information Selective Disclosure

  29. Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information Selective Disclosure

  30. Land patterns of power components TI Information Selective Disclosure

  31. Connecting Bypass Capacitors Connecting to high frequency bypass caps: This assumes a connection into internal planes Terrible! Long thin traces add inductance and effectively isolate the capacitor Good Keeping vias close to pads minimizes parasitic inductance Better Doubled vias further reduce inductance Best This technique further reduces inductance by reducing the high frequency loop area Super!

  32. Connecting Bypass Capacitors TERRIBLE GOOD

  33. Thank You! Questions? TI Information Selective Disclosure TI Information Selective Disclosure

Related


More Related Content

giItT1WQy@!-/#giItT1WQy@!-/#giItT1WQy@!-/#giItT1WQy@!-/#giItT1WQy@!-/#