Basic Language Constructs of VHDL for Advanced Digital System Design
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Advanced Digital System Design
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Skeleton/syntax of VHDL program,
Elements and program format,
Objects, Data type and operators,
Concurrent Signal Assignment,
Combinational versus sequential circuits,
Signal assignment statements,
conditional signal assignment,
Selected signal assignment,
Conditional versus selected signal assignment statements
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A VHDL program is composed of a collection of
Design Units
A synthesizable VHDL program needs at least two design units:
An
Entity
declaration
An
Architecture
body
Skeleton of typical VHDL program can be best explained by an
example – even_detector as discussed earlier
It describes the
external interface,
or “
outline
” of a circuit – which includes the
name of circuit
and the
names and basic characteristics
of its input and output
ports
In the example,
entity declaration
indicates that name of circuit is –
even_detector
and the circuit has a
3-bit input
port,
a
, and a
1-bit output
port,
even
Simplified
syntax
of an
entity declaration
is
Port declaration contains following
terms:
Port_names,
Mode
Data_type
Mode
term indicates direction of
signal, which can be
in, out
or
inout
The
in
and
out
keywords indicate
that signal flows “into” and “out of”
the circuit respectively
The
inout
keyword indicates that
signal flows in both directions and
that corresponding port is
bidirectional
Mode term can also be
buffer
Port declaration above has 2 parts:
a
port – input signal having data type
std_logic_vector(2
downto
0) which
represents a 3-bit bus
even
port – output port having data
type std_logic
Note that any port with
out
mode cannot
be used as an input signal
It specifies the internal operation (behavioural model) or organization (structural
or dataflow model) of a circuit
In VHDL, we can develop multiple architecture bodies for the same entity
declaration and later choose one body to bind with the entity for
simulation/synthesis
Simplified
syntax
of an
architecture body
is:
First line
shows the
name of body
and the corresponding
entity
It may contain an optional
declarative section
consisting of
declarations of some objects, such as
signals and constants which are used
in architecture description
The example has a declaration of
internal signals:
Main part
of architecture body
consists of
concurrent statements
that describe the operation or
organization of circuit
Design units are fundamental building blocks in VHDL program
When a program is processed, it is broken into individual design
units and each unit is analysed and stored independently.
The 5 kinds of design units are:
Entity Declaration
Architecture Body
Package Declaration
Package Body
Configuration
Entity declaration and Architecture body have been discussed earlier
Package
of VHDL normally contains a collection of
commonly used items such as –
Data types
Subprograms
Components
These items are needed by many VHDL programs
As the name suggests, a
package declaration
consists of
declaration of these items
A
package body
normally contains the
implementation
and
code of the subprograms
In VHDL, many architecture bodies can be associated with
an entity declaration
A
Configuration
specifies which architecture body is to be
bound with the entity declaration
A VHDL
Library
is a place to store the design units
It is mapped into a directory (folder) in the computer’s hard
disk
The software defines the mapping between VHDL library
name and the physical directory
By VHDL default, the design units are stored in a library
named
‘work’.
To facilitate the
synthesis
, IEEE has developed several VHDL
packages, including the
std_logic_1164
package
To use a predefined package, we must include the
library
and
use statements
before the entity declaration
The first 2 lines of the example are for this purpose:
library ieee;
use ieee.std_logic_1164.all;
The first line invokes a library named
ieee,
and
The second line makes the
std_logic_1164 package
visible to the
subsequent design unit.
We must invoke this library because we want to use some
predefined
data types
,
std_logic
and
std_logic_vector
, of the
std_logic_1164 package
Lexical Elements
- Basic syntactical units in a VHDL program
Comments
Identifiers
Reserved Words
Numbers
Characters
Strings
Comments
Starts with 2 dashes, --, followed by the text.
Anything after the -- symbol in the same line will be ignored
Comment is for documentation purposes only and has no effect on
code
E.g. – we have added comments to the previous VHDL code:
Identifiers
– name of an
object
in VHDL
Basic
rules
to form an identifier are:
It can contain only
alphabetic letters
,
decimal digits
and
underscores
First character
must be a
letter
(e.g. a,b,c,A,B,C)
Last character
cannot be an
underscore
(__)
Two successive underscores (_ _) are not allowed
Following identifiers are
valid
:
A10, next_state, NextState, mem_addr_enable
Following identifiers
violate the rules
and will cause syntax
error
sig#3, _ X 1 0 , ‘7segment, X10_, hi_ _there
Identifiers
As VHDL is not case-sensitive, following identifiers are same:
nextstate , NextState , NEXTSTATE, nEXTsTATE
It is a good practice to be consistent with the case
It is also a good practice to use descriptive identifier for better
readability
Reserved Words
Some words are reserved in VHDL to form the basic language
constructs.
These reserved words are:
VHDL to form the basic language constructs.
These reserved words are:
This content delves into the fundamental aspects of VHDL programming, covering topics such as skeleton syntax, entity declaration, port declaration, and architecture body. It explores the structure of VHDL programs, elements, data types, signal assignments, and the difference between combinational and sequential circuits. A detailed explanation with examples is provided to aid in grasping the key concepts of VHDL for designing advanced digital systems.
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Presentation Transcript
UNIT 2 Basic Language Constructs of Basic Language Constructs of VHDL VHDL Advanced Digital System Design
Contents Contents Skeleton/syntax of VHDL program, Elements and program format, Objects, Data type and operators, Concurrent Signal Assignment, Combinational versus sequential circuits, Signal assignment statements, conditional signal assignment, Selected signal assignment, Conditional versus selected signal assignment statements
Skeleton / Syntax of VHDL program Skeleton / Syntax of VHDL program A VHDL program is composed of a collection of Design Units A synthesizable VHDL program needs at least two design units: An Entity declaration An Architecture body Skeleton of typical VHDL program can be best explained by an example even_detector as discussed earlier
Entity Declaration It describes the external interface, or outline of a circuit which includes the name of circuit and the names and basic characteristics of its input and output ports In the example, entity declaration indicates that name of circuit is even_detector and the circuit has a 3-bit input port, a, and a 1-bit output port, even Simplified syntax of an entity declaration is
Entity Declaration Port declaration contains following terms: Port_names, Mode Data_type Mode term indicates direction of signal, which can be in, out or inout The in and out keywords indicate that signal flows into and out of the circuit respectively The inout keyword indicates that signal flows in both directions and that corresponding port is bidirectional Mode term can also be buffer Port declaration above has 2 parts: a port input signal having data type std_logic_vector(2 downto 0) which represents a 3-bit bus even port output port having data type std_logic Note that any port with out mode cannot be used as an input signal
Architecture Body It specifies the internal operation (behavioural model) or organization (structural or dataflow model) of a circuit In VHDL, we can develop multiple architecture bodies for the same entity declaration and later choose one body to bind with the entity for simulation/synthesis Simplified syntax of an architecture body is:
Architecture Body First line shows the name of body and the corresponding entity It may contain an optional declarative section consisting of declarations of some objects, such as signals and constants which are used in architecture description The example has a declaration of internal signals: Main part of architecture body consists of concurrent statements that describe the operation or organization of circuit
Design Units Design units are fundamental building blocks in VHDL program When a program is processed, it is broken into individual design units and each unit is analysed and stored independently. The 5 kinds of design units are: Entity Declaration Architecture Body Package Declaration Package Body Configuration Entity declaration and Architecture body have been discussed earlier
Design Units Package Declaration Package of VHDL normally contains a collection of commonly used items such as Data types Subprograms Components These items are needed by many VHDL programs As the name suggests, a package declaration consists of declaration of these items A package body normally contains the implementation and code of the subprograms
Design Units Configuration In VHDL, many architecture bodies can be associated with an entity declaration A Configuration specifies which architecture body is to be bound with the entity declaration
Library A VHDL Library is a place to store the design units It is mapped into a directory (folder) in the computer s hard disk The software defines the mapping between VHDL library name and the physical directory By VHDL default, the design units are stored in a library named work . To facilitate the synthesis, IEEE has developed several VHDL packages, including the std_logic_1164 package To use a predefined package, we must include the library and use statements before the entity declaration
Library The first 2 lines of the example are for this purpose: library ieee; use ieee.std_logic_1164.all; The first line invokes a library named ieee, and The second line makes the std_logic_1164 package visible to the subsequent design unit. We must invoke this library because we want to use some predefined data types, std_logic and std_logic_vector, of the std_logic_1164 package
Lexical Elements and Program Format Lexical Elements - Basic syntactical units in a VHDL program Comments Identifiers Reserved Words Numbers Characters Strings
Lexical Elements and Program Format Comments Starts with 2 dashes, --, followed by the text. Anything after the -- symbol in the same line will be ignored Comment is for documentation purposes only and has no effect on code E.g. we have added comments to the previous VHDL code:
Lexical Elements and Program Format Identifiers name of an object in VHDL Basic rules to form an identifier are: It can contain only alphabetic letters, decimal digits and underscores First character must be a letter (e.g. a,b,c,A,B,C) Last character cannot be an underscore (__) Two successive underscores (_ _) are not allowed Following identifiers are valid: A10, next_state, NextState, mem_addr_enable Following identifiers violate the rules and will cause syntax error sig#3, _ X 1 0 , 7segment, X10_, hi_ _there
Lexical Elements and Program Format Identifiers As VHDL is not case-sensitive, following identifiers are same: nextstate , NextState , NEXTSTATE, nEXTsTATE It is a good practice to be consistent with the case It is also a good practice to use descriptive identifier for better readability
Lexical Elements and Program Format Reserved Words Some words are reserved in VHDL to form the basic language constructs. These reserved words are:
Lexical Elements and Program Format VHDL to form the basic language constructs. These reserved words are:
