Approximate Computing in Hardware Design: A Comprehensive Overview
Axilog: Language Support for
Approximate Hardware Design
DATE 2015
Georgia Institute of Technology
Alternative Computing Technologies (ACT) Lab
Approximate computing
Embracing error
•
Relax the abstraction of
near-perfect
accuracy in
general-purpose
computing/communication/storage
•
Allow errors to happen during
computation/communication/storage
–
Improve resource utilization efficiency
•
Energy, bandwidth, capacity, …
–
Improve performance
•
Build
acceptable
systems from
intentionally-made
unreliable
software and hardware components
•
Avoid
overkill
and
worst-case
design
2
Avoiding Worst-Case Design
Approximate Computing
3
Cost
Cost
Physical
Device
Circuit
Architecutre
Compiler
Programming
Language
Application
Microarchitecture
Goals
Design the
first
HDL for
1)
Approximate Hw
Design
2)
Approximate Hw
Reuse
3)
Approximate
Synthesis
Criteria
Approximate HDL shall be
1)
High-level
2)
Automated
3)
Backward compatible
4
Safety in Hardware
5
Axilog Annotations
6
Design Annotations
relax
(relax_local)
restrict
(restrict_global)
Reuse Annotations
approximate
bridge
critical
Design Annotations
7
Relaxing Accuracy Requirements
8
module ripple_carry_adder(a, b, c_in, c_out, s)
…
full_adder f0(a[0], b[0], c_in, w0, s[0])
full_adder f1(a[1], b[1], w0, c_out, s[1])
r
e
l
a
x
(
s
)
;
…
Relaxing Accuracy Requirements
9
module ripple_carry_adder(a, b, c_in, c_out, s)
…
full_adder f0(a[0], b[0], c_in, w0, s[0])
full_adder f1(a[1], b[1], w0, c_out, s[1])
r
e
l
a
x
(
s
)
;
…
Scoping Approximation (relax_local)
10
Scoping Approximation (relax_local)
11
Restricting Approximation
12
Restricting Approximation
13
Restricting Approximation
14
Restricting Approximation Globally
15
module
full_adder(a, b, c_in, c_out, s);
…
a
p
p
r
o
x
i
m
a
t
e
o
u
t
p
u
t
s
;
r
e
l
a
x
(
s
)
;
…
endmodule
…
r
e
s
t
r
i
c
t
_
g
l
o
b
a
l
(
s
[
3
1
:
0
]
)
;
Restricting Approximation Globally
16
module
full_adder(a, b, c_in, c_out, s);
…
a
p
p
r
o
x
i
m
a
t
e
o
u
t
p
u
t
s
;
r
e
l
a
x
(
s
)
;
…
endmodule
…
r
e
s
t
r
i
c
t
_
g
l
o
b
a
l
(
s
[
3
1
:
0
]
)
;
Reuse Annotations
17
Outputs Carrying Approximate Semantics
18
Critical Inputs
19
…
c
r
i
t
i
c
a
l
i
n
p
u
t
r
e
s
e
t
;
c
r
i
t
i
c
a
l
i
n
p
u
t
c
l
o
c
k
;
…
Next State
Logic
State
Register
reset
clock
Output
Logic
Bridging Approximate Wires to Critical Inputs
20
…
and a1(s, a0, a1);
r
e
l
a
x
(
s
)
;
b
r
i
d
g
e
(
s
)
;
multiplexer m0(s, a0, a1, out);
…
Bridging Approximate Wires to Critical Inputs
21
…
and a1(s, a0, a1);
r
e
l
a
x
(
s
)
;
b
r
i
d
g
e
(
s
)
;
multiplexer m0(s, a0, a1, out);
…
Baseline Synthesis Flow
Highest frequency with minimum power and area
22
Relaxability Inference Analysis
Identify the wires which are driving unannotated wires
or annotated with restrict within the module under
analysis
23
Marks any wire that affects a globally restricted wire as
precise
Identify the relaxed outputs of the instantiated
submodules
Safe to approximate gates
Circuit under analysis with Axilog annotations
Approximate Synthesis Flow
24
A
x
i
l
o
g
C
o
d
e
A
x
i
l
o
g
C
o
m
p
i
l
e
r
S
a
f
e
t
o
A
p
p
r
o
x
i
m
a
t
e
G
a
t
e
s
Measurements
25
26
Benchmarks
Arithmetic Computation, Signal Processing,
Robotics, Machine Learning, Image Processing
Energy Reduction
27
Area Reduction
28
1
0
%
Q
u
a
l
i
t
y
l
o
s
s
i
s
n
e
a
r
l
y
i
n
d
i
s
c
e
r
n
i
b
l
e
t
o
t
h
e
e
y
e
Y
e
t
p
r
o
v
i
d
e
s
5
7
%
e
n
e
r
g
y
s
a
v
i
n
g
s
0% Quality Loss
5% Quality Loss
10% Quality Loss
Output Quality Degradation in Sobel
29
Energy Reduction for Different PVT Corners
30
Axilog
31
First
HDL for Approximation
•
Design
•
Reuse
•
Automation
•
High-level
•
Backward-compatibility
http://www.act-lab.org/artifacts/axilog
Explore the groundbreaking concepts of approximate computing in hardware design, which involves embracing errors to enhance resource efficiency and performance. Delve into topics such as avoiding worst-case design, criteria for approximate HDL, safety in hardware, and relaxing accuracy requirements for specific modules. Discover how these innovations are revolutionizing the field of hardware design.
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Presentation Transcript
Axilog: Language Support for Approximate Hardware Design Amir Yazdanbakhsh Divya Mahajan Bradley Thwaites Jongse Park Anandhavel Nagendrakumar Sindhuja Sethuraman Kartik Ramkrishnan Nishanthi Ravindran Rudra Jariwala Abbas Rahimi Hadi Esmaeilzadeh Kia Bazargan Georgia Institute of Technology University of Minnesota UC San Diego Georgia Institute of Technology Alternative Computing Technologies (ACT) Lab DATE 2015
Approximate computing Embracing error Relax the abstraction of near-perfect accuracy in general-purpose computing/communication/storage Allow errors to happen during computation/communication/storage Improve resource utilization efficiency Energy, bandwidth, capacity, Improve performance Build acceptable systems from intentionally-made unreliable software and hardware components Avoid overkill and worst-case design 2
Avoiding Worst-Case Design Approximate Computing Generality Application Performance Programming Language Efficiency Compiler Architecutre Microarchitecture Circuit Cost Cost Precision Reliability Determinism Physical Device 3
Criteria Goals Design the first HDL for 1)Approximate Hw Design 2)Approximate Hw Reuse 3)Approximate Synthesis Approximate HDL shall be 1) High-level 2) Automated 3) Backward compatible 4
Safety in Hardware Approximate Precise Precise Datapath Controller Clock 5
Axilog Annotations Design Annotations restrict relax (restrict_global) (relax_local) Reuse Annotations critical bridge approximate 6
Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); 8
Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); 9
Scoping Approximation (relax_local) module full_adder (a, b, c_in, c_out, s) relax_local (s); full_adder f0 ( ) full_adder f1( ) relax (s[0]); 10
Scoping Approximation (relax_local) module full_adder (a, b, c_in, c_out, s) relax_local (s); full_adder f0 ( ) full_adder f1( ) relax (s[0]); 11
Restricting Approximation Globally module full_adder(a, b, c_in, c_out, s); approximateoutput s; relax (s); endmodule restrict_global(s[31:0]); 15
Restricting Approximation Globally module full_adder(a, b, c_in, c_out, s); approximateoutput s; relax (s); endmodule restrict_global(s[31:0]); 16
Critical Inputs criticalinput reset; criticalinput clock; reset Output Logic State Register Next State Logic clock 19
Bridging Approximate Wires to Critical Inputs and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); 20
Bridging Approximate Wires to Critical Inputs and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); 21
Baseline Synthesis Flow Highest frequency with minimum power and area 22
Relaxability Inference Analysis Circuit under analysis with Axilog annotations Identify the wires which are driving unannotated wires or annotated with restrict within the module under analysis Identify the relaxed outputs of the instantiated submodules Marks any wire that affects a globally restricted wire as precise Safe to approximate gates 23
Approximate Synthesis Flow Axilog Code Axilog Compiler Safe to Approximate Gates 24
Measurements Tools for Synthesis and Energy Analysis Synopsys Design Compiler Synopsys Primetime Timing Simulation with SDF back annotations Cadence NC-Verilog Standard Cell Library TSMC 45-nm multi-Vt Slowest PVT corner (SS, 0.81V, 0C) for baseline results 25
Benchmarks Arithmetic Computation, Signal Processing, Robotics, Machine Learning, Image Processing # Annotations Design: 6 Reuse: 5 FIR # lines: 113 Signal Processing # Annotations Design: 6 Reuse: 3 # Annotations Design: 1 Reuse: 1 Sobel Brent-Kung # lines: 352 Arithmetic Computation # lines: 143 Image Processing # Annotations Design: 1 Reuse: 1 # Annotations Design: 7 Reuse: 3 Kogge-Stone # lines: 353 Arithmetic Computation K-means # lines: 10,985 Machine Learning # Annotations Design: 5 Reuse: 3 # Annotations Design: 5 Reuse: 4 Wallace Tree # lines: 13,928 Arithmetic Computation ForwardK # lines: 18,282 Robotics # Annotations Design: 4 Reuse: 3 # Annotations Design: 8 Reuse: 4 Neural Network # lines: 21,053 Machine Learning InverseK # lines: 22,407 Robotics 26
Energy Reduction 2.0 Error 10% Error 5% 1.9 1.8 Energy Reduction 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 27
Area Reduction 2.6 Error 10% Error 5% 2.4 2.2 Area Reduction 2.0 1.8 1.6 1.4 1.2 1.0 28
Output Quality Degradation in Sobel 0% Quality Loss 5% Quality Loss 10% Quality Loss 10% Quality loss is nearly indiscernible to the eye Yet provides 57% energy savings 29
Energy Reduction for Different PVT Corners 100% (SS, 0.81V, 125 C) (SS, 0.81V, 0 C) 90% 80% Energy Reduction 70% 60% 50% 40% 30% 20% 10% 0% 30
First HDL for Approximation Design Reuse Automation High-level Backward-compatibility Axilog Area Energy Savings Code Reduction Annotations 1.9 54% 2-12 http://www.act-lab.org/artifacts/axilog 31
