Achieving Deterministic Latency in JESD204B Links
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JESD204B links are the latest trend in data-converter digital interfaces.
These links take advantage of high speed serdes technology to offer
many compelling benefits including improved channel densities and
simplified board layouts. JESD204B expands upon existing JESD204
standards by including methods for achieving deterministic latency. This
presentation addresses one of the challenges of adopting the new
interface - understanding and designing the link latency.
The concepts and examples presented will enable a system designer to:
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Understand the tradeoff between link latency and tolerance to link delay
variation
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Guarantee deterministic latency across the JESD204B link
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Use a formulaic and procedure-based approach to design the link latency
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Defining latency in a JESD204B link
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Deterministic latency intro
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Guaranteeing deterministic latency
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Steps to achieve deterministic latency
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Verifying deterministic latency
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Bonus!
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Latency is defined as the total time (in seconds or clock cycles) it takes
a signal to travel from Point A to Point B
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In a system:
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Point A might be the input to the ADC
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Point B might be the output of the DAC
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In a JESD204B link:
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Point A is the input to the JESD204B transmitter
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Point B is the output of the JESD204B receiver’s elastic buffer
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Device dependent
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SYSREF propagation delay
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JESD link layer
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Serdes implementation
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Board level
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Channel (trace length, vias, connectors)
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SYSREF propagation delay
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Clock propagation delay
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Data is sent over serdes lanes
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Each device receives a “SYSREF” signal
to align LMFCs in each device
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Each device receives a “device clock”
which is essentially the sample clock
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The device clock captures the SYSREF
signal so setup and hold times must be met
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”
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The most important aspect of deterministic latency is that the latency
should
stay constant from system startup to startup.
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Having “deterministic latency” does not necessarily mean the latency is
known
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How do we achieve deterministic latency?
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JESD204B defines two mechanisms for deterministic latency called
“subclasses”
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Applications sensitive to latency
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Digital pre-distortion (DPD) control loops
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Automatic gain control loops (AGC)
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Defensive counter measures
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Any system that requires multi-device synchronization
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Multi-antenna communications systems
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Phased array radar
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Magnetic Resonance Imaging (MRI)
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Sequence of events for subclass 1:
1.
SYSREF is sent to all devices at the same point in time to align their local
multi-frame clocks
2.
All transmitters issue an /A/ or /R/ character at the same point in time based
on the LMFC clock edge.
- Channel and device variations will skew the lanes relative to each other
3.
As each RX receives the /A/ or /R/ character, it starts to buffer it’s data
4.
Once all RXs receive their /A/ or /R/ character and the “buffer release point”
has been reached (e.g. LMFC rising edge), all RXs release their data from
the buffer which is now time aligned
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From step 2 on previous slide, each transmitter sends the /A/ or /R/ character at
the same point in time by using the initial lane alignment sequence
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All transmitters transmit the ILA starting at an LMFC rising edge
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The /A/ or /R/ characters are the trigger signal for deterministic latency
1. SYSREF is used
to align LMFCs
2. After SYNC is
received, all lanes
send ILAS on next
LMFC edge
3. Each lane starts
buffering it’s data
when it receives
the trigger (R or A
char)
4. All lanes are
released on the
next LMFC edge
and are now
aligned
Deterministic Latency Visual
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There are two requirements needed to guarantee deterministic latency
from startup to startup:
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Guarantee the LMFCs in each device are aligned (or have constant
phase difference) every time the system starts
2.
Set release point to occur after the latest arriving lane by:
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Having total link delay less than the LMFC period
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Setting a buffer release point that occurs after all lanes have arrived
This is what the standard expects,
but it’s not always possible based on
hardware tradeoffs (smaller buffers)!
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The LMFCs need to be aligned in each device to create a known timing
reference point
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All devices should receive SYSREF in unison every time the system starts
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SYSREF must meet setup and hold times relative to device clocks
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Technically the LMFCs can be misaligned, but the phase difference
needs to be the same every time the system starts
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The standard says that the total link delay should be less than the
LMFC period, so the easy choice is to set the release point at the
LMFC edge
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The LMFC period is decided by the linerate, F (octets per frame), and K (frames per
multi-frame)
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LMFC period = 10 * F * K / Linerate
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10 = number of bits per octet
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For example, if F = 8, K = 16, and the linerate is 7372.8 Mbps, then the LMFC period
is 173.6 ns.
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In the example, if the total link delay is less than 173.6 ns then the LMFC period
can be chosen as the release point
What happens if the total link delay is greater than 173.6 ns?
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The elastic buffer release point can be shifted from the LMFC rising
edge by using the RBD parameter
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RBD is defined as a shift in the elastic buffer release point from the
LMFC rising edge by “RBD” frame periods
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So an RBD setting of 4 shifts the release point 4 frame cycles from the
LMFC rising edge
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Frame period = 10 * F / Linerate
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RBD must be between 1 and K.
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RBD of K corresponds to the LMFC edge
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RBD can be used for:
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RBD is used to release the buffer earlier to achieve minimum latency
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RBD is used to shift the release point away from the area of uncertainty
near the total link delay
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Consider the following scenario:
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The LMFC period is 50 ns
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The delay for each lane is 100 ns +/- 10 ns (90 ns to 110 ns)
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Assume the buffer release point is set to the
LMFC clock rising edge
Why is there variation on
the data delay?
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Buffer releases on
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In this example, the latency IS NOT deterministic because it is not
consistent from startup to startup
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How do we avoid this scenario?
1.
Calculate the expected maximum lane delay
2.
Choose a release point that occurs after the maximum lane delay
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Set RBD = K/2
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Release Point occurs “RBD” frame
cycles after the LMFC boundary
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Deterministic latency can be achieved using this three step process
1.
Determine Alignment of LMFCs
2.
Calculate expected link delay (accounting for variation)
3.
Choose release point that provides margin against error
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Things to consider:
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Propagation delay of SYSREF and device clocks across board
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Purposefully added delays to SYSREF, such as analog delays or dynamic
digital delays (like in LMK04828)
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Delays from SYSREF input pins to resetting of LMFC (internal to devices)
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The “SYSREF pin to LMFC reset” timing may be different for each
device
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Some datasheets will specify SYSREF to LMFC timing for various
modes (e.g. DAC38J84) and this delay needs to be added to the LMFC
delay.
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These delays will come from the datasheet
or need to be measured or calculated
LMFC alignment between TX and
RX has already been determined
Variations occur due to device
variances (specified in datasheet)
or due to PVT effects
Total Link Delay = t
TX_SER
+ t
LANE
+ t
RX_DESER
+/- t
VARIANCE
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Choose release point that
guarantees enough
margin around the
expected lane arrival
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We have done the following:
1.
Determined LMFC alignment between TX and RX
2.
Calculated total link delay
3.
Determined the appropriate buffer release point
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The total link latency can be calculated using the following formula
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“n” is the number of whole RX multi-frames traversed for the case
where the total link delay exceeds one LMFC cycle
Link Latency = (n * K + RBD) * T
FRAME
+ (t
RX_LMFC
– t
TX_LMFC
)
1
2
n = 2
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1.
Generate a pulse with FPGA
2.
Capture FPGA pulse
with ADC
3.
Output ADC’s MSB from
FPGA
4.
Observe relative timing on scope
5.
Power up the system many times to
confirm the relative timing stays constant
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ADC = ADC16DX370 (16-bit, dual channel, 370 MSPS)
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Device clock = 370 MHz (2.7 ns)
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JESD204B Parameters
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L = 4, M = 2, F = 1, S = 1, K = 32
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Frame cycle = 10 * F / Linerate = 10 * 1 / 3700 Mbps = 2.7 ns
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LMFC cycle = Frame cycle * K = 2.7 ns * 32 = 86.4 ns
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FPGA
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Device clock = 92.5 MHz (10.8 ns)
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Per the previous slides, the latency is calculated as
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For this experiment the following parameters apply
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All units in Frame clock cycles
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t
RX_LMFC
= 28, t
TX_LMFC
= 3.5, n = 2, K = 32, RBD=28
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Link Latency = 116.5 frame clock cycles
•
The following also extend the latency
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ADC16DX370 core latency = +12.5
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DEVCLK routing skew and MSB output routing delay = +1.4
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SYSREF/DEVCLK sampling skew = +1.5
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Additional receiver processing delays
•
+3 rx_tdata release delay (for earliest sample in the 4-sample set output each period of 92.5MHz clock.
This delay may instead be +4)
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+4 latching MSBs before output (at Fs/4 rate)
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•
Calculated latency for
this setup is 138.9 frame cycles
•
Measured latency is
379.6 ns / 2.7 ns = 140.4 cycles
•
Note: Would have been better to
use a short pulse as test signal to
avoid confusion over correct output
pulse
Latency=379.6ns
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1.
Setup a test similar to the one shown to observe relative delays
2.
Vary RBD until a 1 LMFC period latency jump is observed
3.
Choose release point by taking the last RBD value before the latency
jump was observed and add the expected latency variation to that
value (plus extra margin)
Release
Point
Release
Point
Release
Point
Release
Point
Release
Point
Release
Point
Total Latency
Optimal Release Point
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49
JESD204B links utilize high-speed serdes technology to provide benefits like improved densities and simplified layouts. This presentation discusses understanding and designing link latency, offering insights into achieving deterministic latency and managing link delay variations.
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Presentation Transcript
Achieving Deterministic Latency in a JESD204B Link June 1, 2014
Abstract JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high speed serdes technology to offer many compelling benefits including improved channel densities and simplified board layouts. JESD204B expands upon existing JESD204 standards by including methods for achieving deterministic latency. This presentation addresses one of the challenges of adopting the new interface - understanding and designing the link latency. The concepts and examples presented will enable a system designer to: Understand the tradeoff between link latency and tolerance to link delay variation Guarantee deterministic latency across the JESD204B link Use a formulaic and procedure-based approach to design the link latency 2
Table of Contents Defining latency in a JESD204B link Deterministic latency intro Guaranteeing deterministic latency Steps to achieve deterministic latency Verifying deterministic latency Bonus!
What is Latency? Latency is defined as the total time (in seconds or clock cycles) it takes a signal to travel from Point A to Point B In a system: Point A might be the input to the ADC Point B might be the output of the DAC In a JESD204B link: Point A is the input to the JESD204B transmitter Point B is the output of the JESD204B receiver s elastic buffer
JESD204B Latency Influencers Device dependent SYSREF propagation delay JESD link layer Serdes implementation Board level Channel (trace length, vias, connectors) SYSREF propagation delay Clock propagation delay
JESD204B System Diagram (Subclass 1) Data is sent over serdes lanes Each device receives a SYSREF signal to align LMFCs in each device Each device receives a device clock which is essentially the sample clock The device clock captures the SYSREF signal so setup and hold times must be met
Latency Definitions Link Delay delay from when the sampled parallel data is input to the serializer at the transmitter (ADC/FGPA) until the same data is presented at the input to the elastic buffer in the receiver (FPGA/DAC)
Latency Definitions Link Latency the latency from when the sampled parallel data is input to the serializer at the transmitter (ADC/FPGA) until the same data is available in parallel form at the output of the elastic buffer in the receiver (FPGA/DAC)
Which one is Deterministic Latency referring to?
Which block enables Deterministic Latency? Why?
What is Deterministic Latency? Wikipedia: A deterministic system is a system in which no randomness is involved in the development of future states of the system. A deterministic model will thus always produce the same output from a given starting condition or initial state. The most important aspect of deterministic latency is that the latency should stay constant from system startup to startup. Having deterministic latency does not necessarily mean the latency is known How do we achieve deterministic latency? JESD204B defines two mechanisms for deterministic latency called subclasses
JESD204B Subclasses Subclass Subclass 0 Mechanism for Deterministic Latency No support for deterministic latency (backward compatible with JESD204A). SYSREF signal is used to align LMFCs within all TX and RX devices. SYNC signal is used to align LMFCs, eliminating the need for SYSREF . LMFC is aligned based on when the SYNC signal is received from each data converter device. Complex timing means that this will only work below 500 MSPS. Subclass 1 Subclass 2
Which Systems May Need Deterministic Latency? Applications sensitive to latency Digital pre-distortion (DPD) control loops Automatic gain control loops (AGC) Defensive counter measures Any system that requires multi-device synchronization Multi-antenna communications systems Phased array radar Magnetic Resonance Imaging (MRI)
How Does JESD204B Achieve Deterministic Latency? Sequence of events for subclass 1: 1. SYSREF is sent to all devices at the same point in time to align their local multi-frame clocks 2. All transmitters issue an /A/ or /R/ character at the same point in time based on the LMFC clock edge. - Channel and device variations will skew the lanes relative to each other 3. As each RX receives the /A/ or /R/ character, it starts to buffer it s data 4. Once all RXs receive their /A/ or /R/ character and the buffer release point has been reached (e.g. LMFC rising edge), all RXs release their data from the buffer which is now time aligned
Initial Lane Alignment Sequence From step 2 on previous slide, each transmitter sends the /A/ or /R/ character at the same point in time by using the initial lane alignment sequence All transmitters transmit the ILA starting at an LMFC rising edge The /A/ or /R/ characters are the trigger signal for deterministic latency
Deterministic Latency Visual 1. SYSREF is used to align LMFCs received, all lanes send ILAS on next LMFC edge when it receives the trigger (R or A char) 4. All lanes are released on the next LMFC edge 2. After SYNC is 3. Each lane starts buffering it s data and are now aligned x
Guaranteeing Deterministic Latency
How Do We Guarantee Deterministic Latency? There are two requirements needed to guarantee deterministic latency from startup to startup: 1. Guarantee the LMFCs in each device are aligned (or have constant phase difference) every time the system starts 2. Set release point to occur after the latest arriving lane by: Having total link delay less than the LMFC period Setting a buffer release point that occurs after all lanes have arrived This is what the standard expects, but it s not always possible based on hardware tradeoffs (smaller buffers)!
1. Aligning the LMFCs in Each Device The LMFCs need to be aligned in each device to create a known timing reference point All devices should receive SYSREF in unison every time the system starts SYSREF must meet setup and hold times relative to device clocks Technically the LMFCs can be misaligned, but the phase difference needs to be the same every time the system starts
2. Set Release Point to Occur After the Latest Arriving Lane The standard says that the total link delay should be less than the LMFC period, so the easy choice is to set the release point at the LMFC edge The LMFC period is decided by the linerate, F (octets per frame), and K (frames per multi-frame) LMFC period = 10 * F * K / Linerate 10 = number of bits per octet For example, if F = 8, K = 16, and the linerate is 7372.8 Mbps, then the LMFC period is 173.6 ns. In the example, if the total link delay is less than 173.6 ns then the LMFC period can be chosen as the release point What happens if the total link delay is greater than 173.6 ns?
Buffer Release Point The elastic buffer release point can be shifted from the LMFC rising edge by using the RBD parameter RBD is defined as a shift in the elastic buffer release point from the LMFC rising edge by RBD frame periods So an RBD setting of 4 shifts the release point 4 frame cycles from the LMFC rising edge Frame period = 10 * F / Linerate RBD must be between 1 and K. RBD of K corresponds to the LMFC edge RBD can be used for: RBD is used to release the buffer earlier to achieve minimum latency RBD is used to shift the release point away from the area of uncertainty near the total link delay 24
What Happens with Incorrect Release Point? Why is there variation on the data delay? Consider the following scenario: The LMFC period is 50 ns The delay for each lane is 100 ns +/- 10 ns (90 ns to 110 ns) Assume the buffer release point is set to the LMFC clock rising edge
The latest arriving lane arrives at 90 ns Buffer releases on LMFC rising edge 50 ns Data delay is 90 ns Total latency is 100 ns
The latest arriving lane arrives at 110 ns Buffer releases on next LMFC rising edge 50 ns Data delay is 110 ns Total latency is 150 ns
Incorrect Release Point In this example, the latency IS NOT deterministic because it is not consistent from startup to startup How do we avoid this scenario? 1. Calculate the expected maximum lane delay 2. Choose a release point that occurs after the maximum lane delay
Using RBD to shift the release point Release Point occurs RBD frame cycles after the LMFC boundary Set RBD = K/2 50 ns RBD Data delay is 110 ns Total latency is 125 ns for all cases
3-Step Process for Deterministic Latency Deterministic latency can be achieved using this three step process 1.Determine Alignment of LMFCs 2.Calculate expected link delay (accounting for variation) 3.Choose release point that provides margin against error
Step 1: Determine Alignment of LMFCs Things to consider: Propagation delay of SYSREF and device clocks across board Purposefully added delays to SYSREF, such as analog delays or dynamic digital delays (like in LMK04828) Delays from SYSREF input pins to resetting of LMFC (internal to devices)
LMFC Alignment Between Devices The SYSREF pin to LMFC reset timing may be different for each device Some datasheets will specify SYSREF to LMFC timing for various modes (e.g. DAC38J84) and this delay needs to be added to the LMFC delay.
Step 2: Calculate Link Delay Variations occur due to device variances (specified in datasheet) or due to PVT effects These delays will come from the datasheet or need to be measured or calculated Total Link Delay = tTX_SER + tLANE + tRX_DESER +/- tVARIANCE LMFC alignment between TX and RX has already been determined
Step 3: Choose Buffer Release Point Choose release point that guarantees enough margin around the expected lane arrival
Summary of Calculation We have done the following: 1. Determined LMFC alignment between TX and RX 2. Calculated total link delay 3. Determined the appropriate buffer release point 2 3 1
Total Link Latency The total link latency can be calculated using the following formula n is the number of whole RX multi-frames traversed for the case where the total link delay exceeds one LMFC cycle Link Latency = (n * K + RBD) * TFRAME + (tRX_LMFC tTX_LMFC) n = 2 1 2
Deterministic Latency Test Setup 1. Generate a pulse with FPGA 2. Capture FPGA pulse with ADC 3. Output ADC s MSB from FPGA 4. Observe relative timing on scope 5. Power up the system many times to confirm the relative timing stays constant
Device Setup for Test ADC = ADC16DX370 (16-bit, dual channel, 370 MSPS) Device clock = 370 MHz (2.7 ns) JESD204B Parameters L = 4, M = 2, F = 1, S = 1, K = 32 Frame cycle = 10 * F / Linerate = 10 * 1 / 3700 Mbps = 2.7 ns LMFC cycle = Frame cycle * K = 2.7 ns * 32 = 86.4 ns FPGA Device clock = 92.5 MHz (10.8 ns)
Additional Delays in System Account for non-device related delays in calculations O-Scope 12in. Coax 1.6ns Ch.A Input Pulse Splitter 12in. Coax 1.6ns 3in. Rogers4350 0.5ns 18in. Coax 2.3ns ADC FPGA Ch.B 2in. Rogers4350 0.3ns Total Added Latency (due to routing) = (1.6+0.5+2.3)- (1.6)+(1.3-0.3) = 3.8ns LMK 8in. Rogers4350 1.3ns
Latency Calculation Per the previous slides, the latency is calculated as Link Latency = (n * K + RBD) * TFRAME + (tRX_LMFC tTX_LMFC) For this experiment the following parameters apply All units in Frame clock cycles tRX_LMFC = 28, tTX_LMFC = 3.5, n = 2, K = 32, RBD=28 Link Latency = 116.5 frame clock cycles The following also extend the latency ADC16DX370 core latency = +12.5 DEVCLK routing skew and MSB output routing delay = +1.4 SYSREF/DEVCLK sampling skew = +1.5 Additional receiver processing delays +3 rx_tdata release delay (for earliest sample in the 4-sample set output each period of 92.5MHz clock. This delay may instead be +4) +4 latching MSBs before output (at Fs/4 rate) Total Calculated Latency = 116.5 + 12.5 + 1.4 + 1.5 + 7 = 138.9 cycles
Result Calculated latency for this setup is 138.9 frame cycles Latency=379.6ns Measured latency is 379.6 ns / 2.7 ns = 140.4 cycles Note: Would have been better to use a short pulse as test signal to avoid confusion over correct output pulse
Whats the easiest way to achieve deterministic latency? 1. Setup a test similar to the one shown to observe relative delays 2. Vary RBD until a 1 LMFC period latency jump is observed 3. Choose release point by taking the last RBD value before the latency jump was observed and add the expected latency variation to that value (plus extra margin) Release Release Release Release Release Release Point Point Point Point Point Point Total Latency Optimal Release Point
End! 49
