Understanding Different Types of Memory Technologies in Computer Systems
Explore the realm of memory technologies with an overview of ROM, RAM, non-volatile memories, and programmable memory options. Delve into the intricacies of read-only memory, volatile vs. non-volatile memory, and the various types of memory dimensions. Gain insights into the workings of ROM, including the permanent memory details and internal components. Unravel the functioning of Mask ROMs, PROMs, and UV EPROMs, each offering unique characteristics in the field of computer memory.
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COMP541 Memories - I Montek Singh Mar {21, 23}, 2018 1
Topics Overview of Memory Types Read-Only Memory (ROM): PROMs, FLASH, etc. Random-Access Memory (RAM) Static today Dynamic next 2
Types of Memory Many dimensions Read Only vs. Read/Write (or write seldom) Volatile vs. Non-Volatile Requires refresh or not Look at ROM first to examine interface 3
Non-Volatile Memory Technologies Mask (old) ROM read-only memory Fuses (old) PROM programmable read-only memory Erasable EPROM erasable programmable read-only memory Electrically erasable EEPROM electrically-erasable programmable read-only memory today called FLASH! used everywhere! 4
Details of ROM Memory that is permanent k address lines 2k items n bits 5
Notional View of Internals Main components: decoder for address decoding select one row wired-OR per bit OR s together minterms ORing done by connecting outputs of effectively tristate buffers 6
ROM after programming Remember: OR is a wired OR output is 1 if any of the rows with an intact fuse is 1 0 otherwise 8
Mask ROMs Oldest technology Originally mask used as last step in manufacturing Specify metal layer (connections) Used for volume applications Long turnaround Used for applications such as embedded systems and, in the old days, boot ROM but cheap to mass produce! 9
Programmable ROM (PROM) Early ones had fusible links High voltage would blow out links Fast to program Single use 10
UV EPROM Erasable PROM Common technologies used UV light to erase complete device Took about 10 minutes Holds state as charge in very well insulated areas of the chip Nonvolatile for several (10?) years 11
EEPROM Electrically Erasable PROM Similar technology to UV EPROM Erased in blocks by higher voltage Programming is slower than reading Today s flavor is called flash memory Digital cameras, MP3 players, BIOS Limited life Some support individual word write, some block Our boards have it: A flash memory chip on our Nexys boards Has a boot block that is carefully protected We will learn to use it in upcoming labs 12
How Flash Works Special transistor with floating gate This is part of device surrounded by insulation So charge placed there can stay for years Aside: some newer devices store multiple bits of info in a cell Interested in this? Let s cover briefly 13
Flash Add an extra gate to an nMOS transistor a float gate below the actual control gate float gate is isolated from everything else can hold electrons for a while charge on float gate determines bit value stored electrons deposited negative charge does not allow transistor to turn on if no electrons on float gate transistor can be turned on by the control gate two oxide barriers between control and floating gates between floating gate and channel (thin barrier) https://en.wikipedia.org/wiki/Flash_memory 14
Flash: Reading and Erasing Reading apply 1 to control gate, and 1 between source and drain if floating gate is empty, transistor will be on (current flows) if floating gate has electrons, they will mask the control 1 no current will flow Erasing apply HIGH negative voltage to control pushes electrons out of floating gate, through the oxide, into the channel erases the value to 1 oxide barrier is thin high voltage overcomes it https://en.wikipedia.org/wiki/Flash_memory 15
Flash: Writing Writing basic idea is to pull in electrons into the floating gate, through the oxide, from the channel high voltage needed to pull electrons through oxide barrier two methods apply HIGH negative voltage to control gate pulls electrons from the channel (via quantum tunneling) apply HIGH voltage across channel (between source and drain), and a normal 1 to the control creates high-velocity electrons ( hot electrons ) going from source to drain 1 at the control pulls them into the floating gate https://en.wikipedia.org/wiki/Flash_memory 16
Flash: Erasing/Writing speeds Erasing/Writing wear causes wear on the cell high voltage used slowly damage the oxide often 10,000 erase/write cycles is the limit For fast write speeds must have empty blocks available speeds slows down as memory fills thus, garbage collection is important overprovisioning used in SSDs https://en.wikipedia.org/wiki/Flash_memory 17
Read/Write Memories Flash is obviously writeable But not meant to be written rapidly (say at CPU rates) And often writing needs erasure of entire blocks For frequent writing, use RAM 18
Random Access Memories So called because it takes same amount of time to address any particular location Not entirely true for modern DRAMs, but somewhat true First look at asynchronous static RAM reading and writing typically controlled by handshakes clock may still be present, but actions controlled by handshake signals 19
Simple View of RAM Typical parameters: some word size n some capacity 2k k bits of address line Need a line to specify reading or writing typically only one wire needed sometimes two separate ones 20
Example: 1K x 16 memory RAM comes in variety of sizes from 1-bit wide main issue is no. of pins available on chip Memory size often specified in bytes This would be 2KB memory 10 address lines (=1K locations) 16 data lines (=2 bytes/location) 21
Writing Sequence of steps Set up address lines Set up data lines Activate write line (e.g., maybe a positive edge) 22
Reading Steps Setup address lines Activate read line Data available soon for asynchronous memory: after simply a specified amount of time for synchronous memory: after a clock edge 23
Chip Select Enable: Usually a line to enable the chip Why? 24
Static vs. Dynamic RAM Different internal implementations: SRAM vs. DRAM DRAM: DRAM stores charge in capacitor Disappears after short period of time Must be refreshed Small size Higher storage density larger capacities SRAM: SRAM easier to use Uses transistors (think of it as latch) Faster More expensive per bit Smaller sizes 27
Structure of SRAM Internally, each bit stored in a latch One memory cell per bit Cell consists of a few transistors Not really a latch made of NANDs/NORs, but logically equivalent Behaves like an SR latch Control logic also need extra logic around the latch to make it work like a memory cell 28
Structure of SRAM Several optimized circuits often used replace a full-fledged SR latch with something simpler, smaller, faster Not really a latch made of NANDs/NORs, but logically equivalent Behaves like an SR latch e.g., a simpler 6-transistor memory cell wordline Select (bitline, bitline ) (B, B ) as well as (C, C ) bitline bitline wordline 29
Example: A Simple Organization Note: In reality, more complex Only one word-line is on at a time 2:4 Decoder bitline2 bitline1 bitline0 wordline3 11 stored bit = 0 stored bit = 1 stored bit = 0 2 Address wordline2 10 stored bit = 1 stored bit = 0 stored bit = 0 wordline1 01 stored bit = 1 stored bit = 1 stored bit = 0 wordline0 00 stored bit = 0 stored bit = 1 stored bit = 1 Data2 Data1 Data0 30
Zoom in: A single bit slice Operation: Cells connected to form 1 bit position (column) Word Select enables one latch from address lines only this cell is writable only this cell is read B (and B ) set by: Read/Write Data In Bit Select Outputs are C and C if enabled, output value of cell if disabled, typically output floating 31
Lets look at a single bit cell bitline wordline stored bit Example: Z bitline =0 bitline = wordline = 1 wordline = 0 stored bit = 0 stored bit = 0 Z 1 bitline = bitline = wordline = 1 wordline = 0 stored bit = 1 stored bit = 1 (a) (b) 32
Bit Slices and Modules Entire column of cells called a bit slice basically a 1-bit wide memory! Module module refers to a single chip of memory 1-bit wide memory chips are quite common! 33
Inside an SRAM Bit Cell Actual implementation does not use a real SR latch! a tinier approximation is used logically behaves very much like an SR latch but much smaller and faster! bitline wordline stored bit bitline bitline wordline 34
16 X 1 RAM Chip Now shows address decoder selects appropriate location 35
Row/Column Layout For larger RAMs: decoder becomes pretty big also run into chip layout issues Typically: larger memories use 2D matrix layout see next slide 36
16 X 1 RAM as 4 X 4 Array Two decoders Row Column Address just broken up Not visible from outside on SRAMs 37
Not the same as 8 X 2 RAM! Minor change in logic and pins Spot the difference! 38
Realistic Sizes Example: 256Kb memory organized 32K X 8 Single-column layout would need 15-bit decoder with 32K outputs! Better organization: A 2D (i.e., square) layout with: 9-bit row and 6-bit column decoders 40
SRAM Performance Latency and Throughput important Current ones have cycle times in low nanoseconds say 1-2ns (top-end ones even lower) Used as cache (typically on-chip or off-chip secondary cache) Sizes up to 8Mbit or so for fast chips Expensive ones can go a bit bigger Energy/power SRAMs also better for low power vs. DRAMs 41
Wider Memory What if you don t have enough bit width? use multiple chips and side-by-side 42
Larger/Wider Memories Made up from sets of chips Consider a 64K by 8 RAM our building block 43
Larger Let s build a larger memory 256K X 8 Decoder for high-order 2 bits Selects chip Look at selection logic Address ranges Tri-state outputs 44
Summary Today we looked at: Quick look at non-volatile memory Static RAM Next topic: Dynamic RAM Complex, largest, cheap Much more design effort to use 45
