Understanding Shared Memory Systems in Computer Architecture
Shared memory systems in computer architecture allow all processors to have direct access to common physical memory, enabling efficient data sharing and communication among processors. These systems consist of a global address space accessible by all processors, facilitating parallel processing but also introducing challenges such as contention and performance degradation. Classifications include Uniform Memory Access (UMA) and Non-Uniform Memory Access (NUMA), each with distinct characteristics and suitability for different applications.
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SHARED MEMORY SYSTEMS From a strictly hardware point of view, shared memory systems describe a computer architecture where all processors have direct (usually bus-based) access to common physical memory. Shared memory parallel computers vary widely, but generally have in common the ability for all processors to access all memories as global address space. It is an efficient means of passing data between programs. Multiple processors can operate independently, but share the same memory resources.
Shared memory consists of a global address space which is accessible by all N-processors. A processor processor by writing into the global memory where the second processor can read it. can communicate with another Therefore, all of the processors share the same memory and have access to it. It is an efficient means of passing data between programs. One program will create a memory portion which other processes (if permitted) can access. Changes in a memory location effected by one processor are visible to all other processors.
In computer architecture, shared memory architecture (SMA) refers to a multiprocessing design where several processors access globally shared memory. Systems processors communicate by reading and writing memory locations. However, there is usually the problem of performance degradation due to contention when several processors try to access the same memory locations. A fast, special interconnection network (e.g. a high- speed bus or cross bar switch) allows any processor to access any part of the memory in parallel.
CLASSIFICATIONS OF SHARED MEMORY Historically, machines have been classified as: Uniform Memory Access (UMA) and Non-Uniform Memory (NUMA), based access time shared memory Access memory upon
Uniform Memory Access (UMA) Uniform Memory Access (UMA) is commonly represented by symmetric multiprocessor (SMP). That is, multiple processors work together on the same task and communicate with each other as needed. UMA includes identical processors with equal access times to memory. UMA gets its name from the fact that each processor must use the same shared bus to access memory, resulting in a memory access time that is uniform across all processors. In UMA, access time remains the same independent of data location within memory. It is sometimes called cache coherent (CC-UMA), cache coherent means if one processor updates a location in shared memory, all other processors know about the update. UMA is suitable for general purpose and time sharing applications by multiple users. It can be used to speed up the execution of a single large program. All processors access shared memory through a bus (or another type of Interconnect).
NON-UNIFORM MEMORY ACCESS (NUMA) Non-Uniform Memory Access (NUMA) is often by physically linking two or more SMPs. One SMP can directly access memory of another SMP. In NUMA, not all processors have equal to access time to memory. In NUMA, if data resides in local memory, access is fast but if data resides in remote memory access is slower. That is under NUMA, a processor can access its own local memory faster than memory local to another processor or memory shared between processors. Memory access time varies with location of data to be accessed.
In NUMA, each processor has its own local memory module that it can access directly with a distinctive performance advantage. At the same time, it can also access any memory module belonging to another processor using a shared bus (or some other types of Interconnect).
NUMA is a method of configuring a cluster of microprocessor in a multiprocessing system so that they can share memory locally, improving performance and the ability of the system to be expanded. NUMA adds an intermediate level of memory shared microprocessors so that all data accesses do not have to travel on the main bus. among a few
Most computers now have multi-core CPUs. Multicore CPUs are also found on smartphones and tablets. The more CPUs or cores a computer has, the more activities it can perform at once, this helps to improve performance. Other cores can be used to perform background tasks to avoid slowing down programs. The advent of dual core CPUs offer dramatically better desktop experience to PCs users.
When multiprocessors are used. For example: dual processor PC with motherboard having two sockets for CPUs as present in some processors. Some other examples are: more computing power is needed, Sun Ultra Enterprise 72 Ultra SPARCIV + Processor 1.5GHZ IBM Power5 AMD Quad Phenom Intel Core i7 Quad Sun Niagara
Examples Dual-Core: AMD Phenom II X2, Intel core Duo Quadcore: AMD Phenom II X4, Intels i5 and i7 Hexa-core: AMD Phenom II X6and Intel core i7 Octa-core: Intel Xeon E7-2820 and AMD FX-8350 Deca-core: Intel Xeon, E7-2850
DISTRIBUTED MEMORY Like memory systems vary widely but they share a common characteristic. shared memory systems, distributed Distributed communication processor memory memory network systems to require a connect inter-
DISTRIBUTED MEMORY Processors have their own local memory. Memory addresses in one processor do not map to another processor, so there is no concept of global address space across all processors. Because each processor has its own local memory, it operates independently. Changes it makes to its local memory have no effect on the memory of other processors. Hence, the concept of cache coherency does not apply. When a processor needs access to data in another processor, it is usually the task of the programmer to explicitly define how and when data is communicated. Synchronization between tasks is likewise the programmer's responsibility. The network "fabric" used for data transfer varies widely, though it can be as simple as Ethernet.
Advantages of Distributed Memory Memory is scalable processors. Increase the number of processors and the size of memory increases proportionately. with the number of Each processor can rapidly access its own memory without interference and without the overhead incurred with trying to maintain global cache coherency. Cost effectiveness: DM can use commodity, off- the-shelf processors and networking.
Disadvantages of Distributed Memory The programmer is responsible for many of the details associated with data communication between processors. It may be difficult to map existing data structures, based on global memory, organization. to this memory Non-uniform memory access times - data residing on a remote node takes longer to access than node local data.
