Design of Multi-Level Gate Circuits Using NAND and NOR Gates

Explore the design and analysis of multi-level gate circuits using NAND and NOR gates, including two-level and multiple-output circuit design. Learn about circuit conversion, alternative gate symbols, AND-OR, OR-AND configurations, and factorization of multi-level gate circuits. Dive into examples and realizations of multi-level gate circuits for a comprehensive understanding of digital circuit design.

• Multi-Level Gate Circuits
• NAND Gates
• NOR Gates
• Circuit Design
• Digital Circuits

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1. UNIT 7 MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES Objectives Study Guide Multi-Level Gate Circuits NAND and NOR Gates Design of Two-Level Circuits Using NAND and NOR Gates Design of Multi-Level NAND- and NOR-Gate Circuits Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-Level, Multiple-Output Circuits 7.7 Multiple-Output NAND and NOR Circuits 7.1 7.2 7.3 7.4 7.5

2. Objectives Topics introduced in this chapter: Design a minimal two-level or multi-level circuit Design or analyze a two-level gate circuit Design or analyze a multi-level gate circuit Convert circuits by adding or deleting inversion bubbles Design a minimal two-level or multiple-output circuit using Karnaugh maps

3. 7.1 Multi-Level Gate Circuits Terminology AND-OR, OR-AND, OR-AND-OR, AND and OR Four-Level Realization of Z

4. 7.1 Multi-Level Gate Circuits Three-Level Realization of Z ( ( D AB = )( E + ) = + + + + Z AB C + D + E FG H ) ( ) + + + C D E ABFG CFG H

5. 7.1 Multi-Level Gate Circuits Example : Multi-Level Design Using AND and OR Gates ( ) ( , 6 , 5 , 1 m ) = , , , 10 13 , 14 , f a b c d Two-level AND-OR gate

6. 7.1 Multi-Level Gate Circuits Factoring Prev. Eq. = + + + ' ' ' ' ' f a c d bc d bcd ' acd ( ) ( ) b + = + ' + ' c d a b cd a Three-level OR-AND-OR gate From 0 s on the Karnaugh map = + + + ' ' ' ' ' ' ' f c d ab c cd a b c ' ' f ( )( )( )( ' ) ' c = + + + + + + ' ' f c d a b c c d a b Two-level OR-AND gate

7. 7.1 Multi-Level Gate Circuits Using( )( ) + + = + X Y X Z X YZ ( ) ( ) = + + ' + ' + ( ' f c d a b c d ) b + + a b ( ) b + ' ' d a )( d ) ' a If we multiply out ( c f = and ' + + + ' ' a d bd c ad bd ( ( ) d ( ) = + + + ' ' ' ' ' d ' + f c d ab c d a b )( ) ( )( ) ' b = + + + + ' ' ' ' ' c d a b c a d Three-level AND-OR-AND gate

8. 7.2 NAND and NOR Gates NAND gate ? = ??? = ? + ? + ? + ?2 + +?? = ?1 ? = ?1?2 ??

9. 7.2 NAND and NOR Gates NOR gate ? = ? + ? + ? = ? ? ? ?2 ?? = ?1 ? = ?1+ ?2+ +??

10. 7.2 NAND and NOR Gates OR realized by using AND and NOT gates

11. 7.2 NAND and NOR Gates NAND gate realization of NOT, AND, and OR gates AND realized by using OR and NOT ? ? = ? + ?

12. 7.3 Design of Two-Level Circuits Using NAND and NOR Gates DeMorgan s laws ?2 ?? = ?1 ?1+ ?2+ + ?? + ?2 + +?? = ?1 ?1?2 ?? Conversion of a sum-of-products to several other two-level forms ' C ( ) ' ' = + + = + + AND-OR NAND-NAND OR-NAND NOR-OR ' ' ' ' F A BC B CD A BC B CD A ( ( ) ( ' ' C + ) ' ' C + = ' ' A BC B CD + )' ' ) ( ) ( ' C ) = + + ' + ' ' ' D A B B D + ( = + ' ' B B

13. 7.3 Design of Two-Level Circuits Using NAND and NOR Gates = + + + + + NOR-NOR-INVERT {[ ( ' )' ( ' )' ' ]' }' F A B C B C D Get F from Karnaugh map, then convert it into F OR-AND ( )( )( ) = + + + + + + ' ' ' F A B C A B C A C D '' ( )( )( ) = + + + + + + ' ' ' A B C A B C A C D ' ' '' ( ) ( ) ( ) = + + + + + + + + ' ' A B C A B C A C D NOR-NOR '' ( ( ) = + + ' ' ' ' ' A B C A BC A CD AND-NOR '' ' )'' ) ( ) ( = ' ' ' ' A B C A BC A CD NAND-AND

14. 7.3 Design of Two-Level Circuits Using NAND and NOR Gates Eight Basic Forms for Two-Level Circuits

15. 7.3 Design of Two-Level Circuits Using NAND and NOR Gates Eight Basic Forms for Two-Level Circuits

16. 7.3 Design of Two-Level Circuits Using NAND and NOR Gates NAND-NOR AND-OR to NAND-NAND Transformation ( ) 2 l : literals ( ) 1,l 1,P P : product terms 2 = + + + + + = F l l P P l l P P 1 2 1 2 1 2 1 2

17. 7.4 Design of Multi-Level NAND- and NOR-Gates Circuits Procedure : multi-level NAND-gate circuits - Simplify the switching function - Design a multi-level circuit of AND and OR gates - Number the levels starting with the output gate as level 1 - Replace all gates with NAND gates, leaving all interconnections between gates unchanged - Leave the inputs to levels 2,4,6, unchanged

18. 7.4 Design of Multi-Level NAND- and NOR-Gates Circuits Example : Multi-Level Circuit Conversion to NAND Gates ( ) e d c b a F + + + = ' ' ' 1 ' + + ' ' f g hi j k

19. 7.5 Circuit Conversion Using Alternative Gate Symbols Alternative Gate Symbols of Inverter Other Alternative Gate Symbols (? + ?) (??) ? ? ? ? ? ? ? ? ?? ? + ?

20. 7.5 Circuit Conversion Using Alternative Gate Symbols NAND Gate Circuit Conversion

21. 7.5 Circuit Conversion Using Alternative Gate Symbols Conversion to NOR Gates

22. 7.5 Circuit Conversion Using Alternative Gate Symbols Conversion of AND-OR Circuits to NAND Gates

23. 7.6 Design of Two-Level,Multiple- Output Circuits Example : Design a circuit with four inputs and three outputs ( ( ( ) ) ) ( ( ( , 7 , 3 m ) = , , , 11 12 , 13 , 14 , 15 , F A B C D m 1 ) ) = , , , , 7 , 3 11 12 , 13 , 15 , F A B C D m 2 = , , , 12 13 , 14 , 15 , F A B C D 3 Karnaugh Maps for Equations

24. 7.6 Design of Two-Level,Multiple- Output Circuits Realization of Equations Multiple-Output Realization of Equations

25. 7.6 Design of Two-Level,Multiple- Output Circuits Example : Design a multiple-output circuit with 4-inputs and 3-outputs = , 7 , 6 , 5 , 3 , 2 2 m f ( ( ( , 9 , 8 , 7 , 6 ) = , 9 , 8 , 7 , 5 , 3 , 2 10 11 , 13 , 15 , f m 1 ) 10 11 , 14 , 15 , f m ) = 13 14 , 15 , 3 Karnaugh Maps for Equations

26. 7.6 Design of Two-Level,Multiple- Output Circuits Minimized equations = + a + ' ' f bd b ' c ab 1 = + f c bd 2 10gates, abd = + + ' ' f bc ab c or 25gate input 3 ' ac d The minimal solution = + ' + + ' ' ' ' f a bd + abd ab c b c 1 = f c a bd 8 gates 22 gate inputs 2 = + + ' ' f bc ab c abd 3

27. 7.6 Design of Two-Level,Multiple- Output Circuits Determination of Essential Prime Implicants for Multiple-Output Realization

28. 7.7 Multiple-Output NAND and NOR Circuits Multi-level Circuits Conversion to NOR Gates ( ) ( ) f e d c b a F + + + = ' ' 1 ( ' ( ) )h = + + + ' ' F a b c g e f 2