Memory Design Overview: SRAM Cell and Bit Slice Organization

This content provides an overview of SRAM (Static Random Access Memory) cell and bit slice organization, explaining the design elements such as SRAM cell augment, D latch tristated output, multiple enable signals, row and bit selection, data input and output, addressing, and memory expansion with multiple bitslices. The illustrations depict the internal structure, operation, and data flow within SRAM cells and bitslices in a digital system. Additionally, it covers address decoding, word width, chip select functionality, and the relationship between bitslices and memory organization.

• Memory Design
• SRAM
• Bit Slice Organization
• Digital System
• Address Decoding

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1. ECE 352 Digital System Fundamentals SRAM Design SRAM Design 1 1

2. SRAM Cell Augment a D Latch Tristated output Multiple enable signals Both selects must be 1 to select the cell SRAM Design must be true for a read SRAM Cell SRAM Cell row select bit select data out (tristated) data in D D Q Q C C RD/WR 0 = write 1 = read must be true for a write 2 2

3. SRAM Bitslice data in (DIN) SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell D D D D D D Q Q Q Q Q Q C C C C C C SRAM Design RD/WR SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell row selects D D D D D D Q Q Q Q Q Q C C C C C C bit select SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell D D D D D D Q Q Q Q Q Q data out (DOUT) C C C C C C 3 3

4. DEC 4 1 SRAM A[1] A[0] 1 3 2 1 0 0 row sel bit sel DIN DIN row sel bit sel SRAM Cell SRAM Cell SRAM Cell SRAM Cell Contains a single bitslice with four rows Data word is only 1 bit wide Plus an address decoder to select the location 4 locations 2 address bits DOUT DOUT R/W R/W row sel bit sel DIN DIN row sel bit sel SRAM Cell SRAM Cell SRAM Cell SRAM Cell DOUT DOUT row selects R/W R/W SRAM Design row sel bit sel DIN DIN row sel bit sel SRAM Cell SRAM Cell SRAM Cell SRAM Cell DOUT DOUT R/W R/W row sel bit sel SRAM Cell SRAM Cell row sel bit sel DIN DIN Bit select = chip select (CS) Bitslice is enabled when SRAM is enabled SRAM Cell SRAM Cell DOUT DOUT R/W R/W bit bit bit sel sel DOUT sel DOUT DOUT R/W DIN R/W DIN R/W DIN DI R/W CS DO 4 4

5. Example: A[1:0] = 01 4 2 SRAM DEC DEC A[1] A[1] A[0] A[0] 1 1 3 2 1 0 0 3 2 1 0 0 SRAM Cell SRAM Cell SRAM Cell Similar to 4 1 SRAM design But with two bitslices Data word is 2 bits wide Bit select = CS Both bitslices enabled when SRAM is enabled Each bitslice contains one bit of every word in the memory A bitslice is a vertical slice of the words SRAM Cell SRAM Cell SRAM Cell SRAM Design SRAM Cell SRAM Cell SRAM Cell ADDRESS 01 SRAM Cell SRAM Cell SRAM Cell bit sel DOUT sel DOUT bit bit sel DOUT DIN DIN R/W R/W DIN R/W CS R/W DI DO DI[0] DO[0] DI[1] DO[1] bitslice 1 bitslice 0 5 5

6. Memory Design: Simple Case Number of rows = number of words Each bitslice contains one bit of every word in the memory For example, bitslice 0 contains bit 0 of each word Decode the memory address to create the row select signals At most one row select can be active at any time or there is contention! Connect bit select input of all bitslices to CS so they are all enabled when the SRAM is enabled This will not be the case later when we examine more complex memory designs SRAM Design 6 6

7. Memory Parameters If you know enough of the design parameters, you can figure out the others Total capacity = <# of words> <word size> Number of address bits = ceil(log2(<# of words>)) Number of rows = <# of words> Row decoder size = <# of address bits> to <# of rows> No column decoder (always one column of words) Number of bitslices = <word size> SRAM Design Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words) 7 7

8. Examples If you know enough of the design parameters, you can figure out the others single column of words Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 1 32 bits 8 K 13 13 : 8 K 8 K 32 None 256 Kbits 8 K = 23 210 = 213 32 8K = 25 213 = 218bits Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words) 8 8

9. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 1 32 bits 8 K 13 13 : 8 K 8 K 32 None 256 Kbits 8 bits 32 5 5 : 32 32 None 256 bits 1 8 Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words) 9 9

10. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 1 32 bits 8 K 13 13 : 8 K 8 K 32 None 256 Kbits 8 bits 32 5 5 : 32 32 None 256 bits 1 8 6 : 64 16 bits 64 6 64 1 16 None 1 Kbit Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words) 10 10

11. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 1 32 bits 8 K 13 13 : 8 K 8 K 32 None 256 Kbits 8 bits 32 5 5 : 32 32 None 256 bits 1 8 6 : 64 16 bits 64 6 64 1 16 None 1 Kbit Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words) 11 11

12. Increasing Number of Words As we increase the number of words in the memory, the address decoder gets bigger Bigger decoder longer paths slower SRAM Design Instead of organizing the memory as a linear array, organize it as a 2D grid of (multi-bit) words Break the address decoder into separate row and column decoders 12 12

13. Coincident Selection Technique to reduce decoder size by breaking up the selection process into two parts A decoder to select the row (row decoder) A decoder to select the column (column decoder) A column is a logical group of bitslices that supplies all of the bits required by the memory s data width Each column may be made up of multiple bitslices! # bitslices per column (of words) = data width SRAM Design A memory cell is only selected if it is selected by both the row decoder and the column decoder 13 13

14. Coincident Selection Example We will show two ways to build a 16 1 SRAM Too small to actually worry about the organization This does become critical for very large SRAMs! 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 SRAM Design One column of 1-bit words Four columns of 1-bit words One bitslice Four bitslices Sixteen rows Four rows 14 14

15. Single-Column 161 SRAM 4 address bits 4:16 row decoder 16 rows 16 row decoder outputs Decodes entire address Each output enables one 1-bit word No column decoder Single bitslice Enabled by chip select DEC 3 2 1 0 15 A[3] A[2] A[1] A[0] SRAM Cell SRAM Cell SRAM Design 0 SRAM Cell SRAM Cell DIN R/Wbit sel DOUT DI R/W CS DO 15 15

16. Multi-Column 161 SRAM 4 address bits 2:4 row decoder 4 rows 4 row decoder outputs Decodes 2 address bits Each output enables four 1-bit words 2:4 column decoder Decodes remaining address bits Four columns, one bitslice each Each decoder output enables one bitslice Enabled by chip select DEC A[1] A[0] 1 3 2 SRAM Cell SRAM Cell SRAM Cell SRAM Cell 0 1 0 SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Design SRAM Cell SRAM Cell SRAM Cell SRAM Cell bit selDOUT bit selDOUT bit selDOUT bit selDOUT DIN DIN DIN DIN DI DO R/W 3 2 1 0 DEC 1 0 EN CS A[3]A[2] 16 16

17. Coincident Selection Example How can we arrange the bits in an 8 2 SRAM? We could also do four columns (eight total bitslices) and two rows Or eight columns (16 total bitslices) and one row SRAM Design One column of 2-bit words Two columns of 2-bit words 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 Two bitslices Four bitslices Eight rows Four rows 17 17

18. Example: A[2:0] = 110 Single-Column 8 2 SRAM 3 address bits 3:8 row decoder 8 rows 8 row decoder outputs Decodes entire address Each output enables one 2-bit word No column decoder Two bitslices Both enabled by chip select DEC 2 7 6 A[2] A[1] A[0] SRAM Cell SRAM Cell 1 5 4 3 0 2 1 SRAM Cell ADDRESS 110 SRAM Cell SRAM Design 0 SRAM Cell SRAM Cell SRAM Cell SRAM Cell bit selDOUT bit selDOUT DIN DIN R/W CS DI[1] DO[1] DI[0] DO[0] 18 18

19. Example: A[2:0] = 110 Multi-Column 8 2 SRAM 3 address bits 2:4 row decoder 4 rows 4 row decoder outputs Decodes 2 address bits Each output enables two 2-bit words 1:2 column decoder Decodes remaining address bits Two columns, two bitslices each Each decoder output enables two bitslices Enabled by chip select DEC A[1] A[0] 1 3 2 SRAM Cell SRAM Cell SRAM Cell SRAM Cell 0 1 0 SRAM Cell ADDRESS 110 SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Design SRAM Cell SRAM Cell SRAM Cell SRAM Cell bit selDOUT bit selDOUT bit selDOUT bit selDOUT DIN DIN DIN DIN DI DO R/W 1 0 DEC IN EN CS A[2] 19 19

20. Coincident Selection Notes The logical view (view from outside) is the SAME Does not change how the memory is used The capacity is still <# of words> <word size> Internally: The # of rows is no longer equal to the # of words The # of bitslices is no longer equal to the word size Each column has a number of bitslices equal to the word size Each column decoder output goes to the same number of bitslices as before Equal to the number of bits per data word SRAM Design Remember: bitslice = vertical slice of bits within column of words! 20 20

21. Examples If you know enough of the design parameters, you can figure out the others two columns of words Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 32 bits 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 8 K 13 1 = 12 8K = 23 210 = 213 32 8K = 25 213 = 218bits 21 21

22. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 32 bits 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 8 K 5 8 2 bits 32 3 : 8 8 2 : 4 64 bits 4 22 22

23. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 32 bits 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 8 K 5 8 2 bits 32 3 : 8 8 2 : 4 64 bits 4 6 : 64 2 bits 512 9 64 16 3:8 8 1 Kbit 210 / 29 = 2 23 23

24. Examples If you know enough of the design parameters, you can figure out the others Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Total Capacity SRAM Design Decode 32 bits 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 8 K 5 8 2 bits 32 3 : 8 8 2 : 4 64 bits 4 6 : 64 2 bits 512 9 64 16 3:8 8 1 Kbit 24 24

25. ECE 352 Digital System Fundamentals SRAM Design SRAM Design 25 25