Understanding Sequential Building Blocks in Digital Logic Design

L7: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2nd ed. Prentice-Hall/Pearson Education, 2005. J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall/Pearson, 2003. Introductory Digital SystemsLaboratory 1

Combinational Logic Review in0 in1 in0 in1 Combinational Circuit inM-1 inN-1 Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value Introductory Digital SystemsLaboratory 2

A Sequential System Inputs Outputs COMBINATIONAL LOGIC Current State Next state Registers Q D Memory element CLK Sequential circuits have memory (i.e., remember the past) The current state is held in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events Introductory Digital SystemsLaboratory 3

A Simple Example Adding N inputs (N-1Adders) in0 in1 in2 inN-1 Using a sequential (serial) approach reset Current_Sum in D Q clk Introductory Digital SystemsLaboratory 4

Implementing State: Bi-stability Vo1 =Vi2 Vi2 = Point C is Metastable Vo1 Vo2 = Vi1 C Vi2 Vo1 Vi1 =Vo2 1 A Vo Points A and B are stable (represent 0 & 1) Vi1 Vo2 Vi2 = A Vi2 =Vo1 C B B Vi1 = Vo2 Vi1 =Vo2 Introductory Digital SystemsLaboratory 5

NOR-based Set-Reset (SR) Flipflop SR = 00, 10 SR = 00, 01 Q S SR = 1 0 S R Q Q Q Q 1 0 Q Q 0 1 R Q 0 0 Q Q SR = 0 1 SR = 0 1 SR = 1 0 1 0 1 0 S Q SR = 11 0 1 1 1 0 0 1 0 SR = 1 1 SR = 1 1 Q Q 0 0 Q Forbidden State R SR = 0 0 SR = 0 0 Hold Reset Set Reset Set R S Q ?? Q Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) this circuit is not clocked and outputs change asynchronously with the inputs L4: 6.111 Spring 2006 Introductory Digital SystemsLaboratory 6

Making a Clocked Memory Element: Positive D-Latch Q D S CLK R sample hold hold sample hold D Q R and S G clock clk A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D) A Latch is level-sensitive: invert clock for a negative latch Introductory Digital SystemsLaboratory 7

Multiplexor Based Positive & Negative Latch 2:1 multiplexor Positive Latch Negative Latch in0 0 out 0 1 1 in1 Q Q D D 1 0 SEL Out = sel * in1 + sel *in0 CLK CLK clk "remember" clk "load" "stored value" "data" Introductory Digital SystemsLaboratory 8

74HC75 (Positive Latch) 2 1D 1Q 16 Q D LE1-2 13 CP 1Q 1 Q L1 3 2D 2Q 15 Inputs Outputs Q D Operating Modes CP 2Q 14 nD nQ nQ LEn-n Q L2 H L L H Data Enabled 6 3D 3Q 10 Q D H H H L LE3-4 4 CP Data Latched L X q q 3Q 11 Q L3 7 4D 4Q 9 Q D CP 4Q 8 Figures by MIT OpenCourseWare. Q L4 Introductory Digital SystemsLaboratory 9

Building an Edge-Triggered Register Negative latch Positive latch Q D D Q D Q D Q D Q QM G G CLK CLK Slave Master CLK D 0 Q QM 1 1 QM 0 D Q CLK CLK Image by MITOpenCourseWare. Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit master-slave flip-flop twice as muchlogic Introductory Digital SystemsLaboratory 10

Latches vs. Edge-Triggered Register Edge triggered device sample inputs on the event edge 7474 Transparent latches sample inputs as long as the clock is asserted D Q Timing Diagram: Clk Positive edge-triggered register D 7475 Clk D Q C Q7474 Clk Level-sensitive latch Q7475 Bubble here for negative edge triggered register Behavior the same unless input changes while the clock is high Introductory Digital SystemsLaboratory 11

Important Timing Parameters Clock: Periodic Event, causes state of memory element to change Clock memory element can be updated on the: rising edge, falling edge, high level, low level Th Tsu Input Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized to be recognized Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Propagation Delay (Tcq for an edge-triggered register and Tdq for alatch) Delay overhead of the memory element Introductory Digital SystemsLaboratory 12

The J-K Flip-Flop S Q J J K Q+ Q+ K R Q 0 0 Q Q 0 1 0 1 1 0 1 0 100 J 1 1 Q Q K Q \Q Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one Introductory Digital SystemsLaboratory 13

J-K Master-Slave Register Sample inputs while clock low Sample inputs while clock high P S Q J S Q P R R Q Q K CLK 1's Catch Set Reset T oggle 100 J Correct Toggle Operation K Clk J Q P Master outputs \ P Q Q K Slave outputs \Q Is there a problem with this circuit? Introductory Digital SystemsLaboratory 14

Pulse Based Edge-Triggered J-K Register Input X Input Output X tpLH Schematic Output J J Q S Q Q R Q K K JK Register Logic Symbol JK Register Schematic Introductory Digital SystemsLaboratory 15

Pulse-Triggered Registers Ways to design an edge-triggered sequential cell: Pulse-Based Register Master-Slave Latches Latch L1 L2 Data Data D Q D Q D Q Clk Clk Clk Clk Clk Short pulse around clock edge Pulse registers are widely used in high-performance microprocessor chips (Sun Microsystems, AMD, Intel, etc.) The can have a negative setup time! Introductory Digital SystemsLaboratory 17

D Flip-Flop vs. Toggle Flip-Flop 1 D Q D Flip-Flop 0 1 Clk 0 1 D 0 1 QN 0 1 0 1 T Q T(Toggle) Flip-Flop 0 0 1 0 Clk T 0 1 QN QN-1 QN-1 1 Introductory Digital SystemsLaboratory 16

Realizing Different Types of Memory Elements Characteristic Equations D: Q+ = D E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q J-K: Q+ = J Q + K Q T: Q+ = T Q + T Q Implementing One FF in Terms of Another Q K J C K Q Q D Q D J C Q D implemented with J-K J-K implemented with D Introductory Digital SystemsLaboratory 17

Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Q Q+ 0 0 1 1 J 0 1 X X K X X 1 0 T 0 1 1 0 D 0 1 0 1 0 1 0 1 D Implementing D FF with a J-K FF: 0 1 Q 1) Start with K-map of Q+ = (D, Q) 0 1 0 2) Create K-maps for J and K with same inputs (D, Q) 0 1 1 Q+ = D 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map D Q 0 D 0 1 0 1 Q 0 1 X X 0 E.g., D = Q= 0, Q+ = 0 then J = 0, K = X X X 1 0 1 1 J =D K = D Introductory Digital SystemsLaboratory 18

Design Procedure (cont.) Implementing J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! JK Q 00 01 11 0 0 0 1 J 10 1 1 1 0 0 1 K Q+ = D = JQ + KQ Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. Introductory Digital SystemsLaboratory 19

System Timing Parameters Combinational Logic In D Q D Q Clk Clk Logic Timing Parameters Register Timing Parameters Tlogic : worst case delay through the combinational logic network Tlogic,cd: contamination or minimum delay through logic network Tcq : worst case rising edge clock to q delay Tcq, cd: contamination or minimum delay from clock to q Tsu: setup time Th: hold time Introductory Digital SystemsLaboratory 20

System Timing (I): Minimum Period CLout Combinational Logic In D Q D Q Clk Clk CLK Th Th IN Tsu TsuTcq Tcq FF1 Tlogic Tcq,cd Tcq,cd CLout Tsu2 Tl,cd T > Tcq + Tlogic + Tsu Introductory Digital SystemsLaboratory 21

System Timing (II): Minimum Delay CLout Combinational Logic In D Q D Q Clk Clk CLK Th Th IN Ts u FF1 Tcq,cd CLout Tl,cd Tcq,cd + Tlogic,cd > Thold Introductory Digital SystemsLaboratory 22

Shift-Register Typical parameters for Positive edge-triggered D Register Tsu 20ns Th 5ns D Tsu 20ns 5ns Th all measurements are made from the clocking event that is, the rising edge of the clock CLK Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Q Shift-register 100 Q0 Q1 DQ IN DQ OUT IN Q0 Q1 CLK CLK Introductory Digital SystemsLaboratory 23