Understanding MOS Transistor Operation Regions and Amplifier Design Principles
Learn about the different operation regions of MOS transistors, including saturation, ohmic, and subthreshold, as well as the design principles for single-stage amplifiers. Explore the effects of Vsb on transistor behavior and basic design exercises for analog circuits.
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INEL 5265 Review I 3/18/2025 Last Lecture MOS Transistor Review (Chap. #3) Transistor Operation Regions & Large Signal Behavior saturation - Vds>Vds(sat) ohmic - Vds<Vds(sat) subthreshold - Vds> 0.2V Small Signal Model low-frequency model frequency dependent model (parasitic capacitances) Single Stage Amplifiers voltage gain terminal impedances Vsb effect! Basic Design Exercises 1 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Single Stage Amplifiers 2 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Single Flow in Transistors It is important to recognize that ac signals can only flow into and out of certain transistor terminals. Rules: The drain can never be an input terminal. The gate can never be an output terminal. 3 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Transistor Design #1 Design the transistor s W/L such that it operates in the saturation region for ID=10 A C W ( ) 2 n OX = I V V DS GS T 2 L W ( )2 A = 10 50 A V V GS T 2 V ID L VG Si VDSSAT=0.2V entonces W/L=5 where Kn=100 A/V2 4 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Transistor Design #2 Design the transistor s W/L such that it operates in the saturation region for ID=10 A and VD = [0.5 - 3.1] V. C W ( ) VDD p OX 2 = | | I V V DS SG T 2 L W ( )2 A VG = 10 50 | | A V V ID SG T 2 V L VD Si VDSSAT min=3.3-3.1=0.2V Entonces W/L=5 where Kp=100 A/V2 VDD=3.3V 5 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Transistor Design #3 Design the transistor s W/L such that it operates in the saturation region for ID=[0.1 10] A and VX(max)=1.2V. This connection is a diode connection and ensures saturation C 2 W ( ) 2 ID n OX = I V V DS GS T L VX W ( 2 . 1 ) A 2 = 10 50 7 . 0 A 2 V L W ( 5 . 0 ) A 2 = 10 50 A V 2 V L where W Kn=100 A/V2 Vt0=0.7V = 4 / 5 L 6 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Common Source Amplifier VDD VDD ID VB Ibias M2 Vout Vout M1 M1 Vin Vin Simplified Schematic Implementation VGS 7 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Common Source Amplifier Typical design approach: 1. Id set by power constraints 2. Vds1(sat) & Vds2(sat) set by output voltage range constraints if any hence (W/L)1 & (W/L)2 3. (W/L)1 set by gain constraints (there might be a need for redesign M1) VDD Large Signal Behavior Vout(min) VDSSAT Typically VDSSAT 0.2V VB M2 Vout(max) VDD-VSDSAT Typically VSDSAT 0.2V Vout Small Signal Behavior Av -gmRout : where Rout=ro2||ro1 M1 Vin 8 Analog Circuit Design
INEL 5265 Review I 3/18/2025 Common Source Amplifier Design the following CS amplifier for the following specifications: Vout = [0.15 2.7] V Psupply < 90 W |Av| > 30 V/V where VT0n=|VT0p|=1.0V K n=100 A/V2 K p=25 A/V2 n= p =0.2V-1 VDD=3.0V VDD VDD = A g R v m OUT V 15 = 3 . 0 V M1 Vin SDSAT Iref =10 A = . 0 V V DSSAT P supply Vout ( )DD V = + I I D ref M3 M2 9 Analog Circuit Design
