Understanding Eyeriss Dataflow for Digital CNN Accelerator
Explore Eyeriss architecture and dataflow including optimizations, spatial architecture, primitive operations, convolution examples, folding techniques, weight and output stationarity concepts, and key terminology.
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Presentation Transcript
Lecture: Eyeriss Dataflow Topics: Eyeriss architecture and dataflow (digital CNN accelerator) 1
Row Stationary Dataflow for one 2D Convolution Example: 4 64x64 inputs; 4x3x3 kernel wts; 8 62x62 outputs; 20 image batch Edge prim: (glb) 64 inp, 3 wts; (reg) 186 MACs psums (124 rg/by) (62 PE) Other prims: (PE) 64 inp, 3 wts; (reg) 186 MACs psums (124 rg/by) (62 PE) The first step is done ~64 times; the second step is done ~122 times Eventually: 4K outputs to global buffer or DRAM 5
Folding May have to fold a 2D convolution over a small physical set of PEs Must eventually take the 4D convolution and fold it into multiple 2D convolutions the 2D convolution has to be done C (input filters) x M (output filters) x N (image batch) times Can exploit global buffer reuse and register reuse depending on which order you do this (note that you have to deal with inputs, weights, and partial sums) 6
Weight Stationary Example: 4 64x64 inputs; 4x3x3 kernel wts; 8 61x61 outputs; 20 image batch Weight Stationary: the weights stay in place Assume that we lay out 3x3 weights across 9 PEs Let the inputs stream over these each weight has to be seen 61x61 times -- no easy way to move the pixels around to promote this 7
Output Stationary Example: 4 64x64 inputs; 4x3x3 kernel wts; 8 61x61 outputs; 20 image batch Output Stationary: the output neuron stays in place Need to use all PEs to compute a subset of a 4D space of neurons at a time can move inputs around to promote reuse 8
Energy Estimates Most ops in convolutional layers Most energy in ALU and RF in convs; most energy in buffer in FC More storage = more delay 10
Summary All about reduced energy and data movement; assume PEs are busy most of the time (except edge effects) Reduced data movement low energy and low area (from fewer interconnects) While Row Stationary is best, need a detailed design space exploration to identify the best traversal thru the 4D array It s not always about reducing DRAM accesses; even global buffer accesses must be reduced More PEs allows for better data reuse, so not terrible even if it means smaller global buffer Convs are 90% of all ops and growing Their best designs are with 256 PEs, 0.5KB regfile/PE, 128KB global buffer; filter/psum/act = 224/24/12 11
WAX 12
References Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks, Y-H. Chen et al., ISCA 2016 Wire-Aware Architecture and Dataflow for CNN Accelerators, S. Gudaparthi et al., MICRO 2019 13
