Understanding Clock System, Memory Features, and Flash Operations in MSP432 MCUs
The MSP432 part 4 training covers the clock system's flexibility, offering a wide range of clock sources for high-speed and low-power operations. It highlights high-accuracy, tunable DCO with various frequency ranges and their calibration. Additionally, it discusses memory features such as flash sizes, speed enhancements, security measures, and dynamic power-down options. The flash operation details include independent bank protection, power savings, and code security options for efficient programming and execution in MSP432 MCUs.
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MSP432 Part 4: Clock System & Memory MCUs Training 1
CS | High-level Features Flexible clock sources & distribution: 5 clocks from 7 sources (2 external, 5 internal) Selections suitable for high-speed & low-power operations Wide range of operating frequency 10kHz to 48 MHz Fine intermediate steps with dividers & tuning Configurable & robust system: Run-time lockable configuration Failsafe mechanism with interrupts for external sources
CS | HF & LF Oscillators Frequency Oscillator s MCLK SMCLK HSMCLK ACLK BCL K Comments 1-48 MHz DCO Internal integrated digitally controlled oscillator. 1-48 MHz HFXT High frequency crystal. Frequency range is SW configurable. HF 24MHz MODOSC Internal osc. option for peripherals such as ADC 5MHz SYSOSC Internal, direct clock for ADC failsafe for HFXT 32kHz LFXT Low-frequency oscillator 32kHz 128kHz REFO Internal low-frequency oscillator. Failsafe* (32kHz) for LFXT LF 10kHz VLO Internal ULP LF oscillator Clock selection for WDT
CS | High-accuracy tune-able DCO 6 tune-able frequency ranges Each range has calibrated center frequency Example: [8-16MHz] range has a calibrated 12MHz center frequency Tune-able within each frequency range Center Frequency +/- 212 steps DCOTUNE register DCO accuracy: Internal resistor: + 2.65 % [Calibrated] External resistor : + 0.4 % [91k +0.1% ] Failsafe for internal resistor mode Frequency Range 16MHz 8MHz 4MHz 1.5 12MHz 24MHz 48MHz 3MHz 6MHz Calibrated Center Frequency 4
Memory | Overview Memory Flash Size Speed 16MHz Features 256kB + 4kB Sector: 4kB Speed boost with 128-bit buffer & pre-fetch Powerful security features 64kB Bank: 8kB 32kB 48MHz Dynamic bank power-down & retention options for low power Robust DriverLib APIs integrated to save application space SRAM 48MHz Lower power execution ROM 8kB 16MHz UART/I2C/SPI Boot-Strap Loader provided BSL *Possible change: programmable BSL in next devices/revisions 5
Memory | Flash } 128kB Bank 1 4kB 4kB 256kB Bank 2 4kB Individually [un-]protected from write/erase INFO 4kB > 105 erase cycles Independent banks simultaneous read/execute and program/erase operations 128-bit buffer Power savings& higher effective speed with ARM s pre-fetch Hardware assisted operations Burst data comparison for fixed patterns (data fill check) Flash program modes with auto-computed parity & auto-verify: Write immediate, 128-bit full word write, or 4*128-bit burst mode Flexible Code security & protection options: Individual Flash IP sector protection, further secured/protected with MPU Up to 4 IP-protection memory zones 6
Memory | RAM Up to 64KB of banked SRAM architecture 8 dynamically configurable banks: Enable/disable banks to optimize active mode power consumption Retain/not retain content in LPM3 to minimize SRAM leakage power consumption SRAM banks Bank 0 enable/retention (always enabled) Bank 1 enable/retention Bank 2 enable/retention . . . Bank 6 enable/retention Bank 7 enable/retention Memory size 8KB 16KB 24KB 56KB 64KB
Memory | Memory Map 256kB + 4kB - Interrupt Vector Table - Application Code 0x00000000 Flash 0x01000000 ROM Peripheral Driver Library 0x20000000 SRAM Bit-Band 0x22000000 Bit-banded SRAM Ultra-low-leakage SRAM - 64kB = 8 x 8kB banks - Bit-banded 0x40000000 Peripherals (Registers) Bit-Band 0x42000000 Bit-banded Peripherals 0xE0000000 Instrumentation, ETM, etc. Peripheral Space - Register directly accessible - Bit-banded
Power, Clock, & Memory | Overall System Design Regulator: DC-DC or LDO DC-DC yields higher efficiency than LDO at higher speed DC-DC requires longer start-up time and transitions from Sleep Modes Flash wait states @ MCLK > 12MHz for VCORE = 0 @ MCLK > 16MHz for VCORE = 1 SystemFrequency VCORE 0 0 0 1 1 LDO/DC-DC* LDO LDO LDO DC-DC DC-DC Flash Wait States VCORE level @ MCLK > 24MHz 0-12MHz 12-16MHz 16-24MHz 24-32MHz 32-48MHz 0 1 1 1 2 9
