SPARC Design Status and Integration Overview
An in-depth look at the SPARC design including functional layout, circuit communications, slow control, integration details, and more. The design features asynchronous PADs, biasing provided by CERN, pixel arrangements, FIFO configurations, TDC counters, and digital inputs/outputs. The article covers various aspects of the design with detailed descriptions and visuals for better understanding.
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Presentation Transcript
Status of the SPARC design Jean SOUDIER Designers: Jean Soudier, Christophe Flouzat Reviewers: Fr d ric Morel Jean.soudier@iphc.cnrs.fr 18/03/2025
Functional layout Asynchronous PADs (Data, Control, Bias, Power) 25 m Design by IRFU Biasing Provided by CERN Pixel 16 m Fixed priority arbiter 1 Fixed priority arbiter 2 Fixed priority arbiter 16 Front -end 3 Front -end 4 Front -end 1 Front -end 2 Front -end 31 Front -end 32 32 pixels 32 pixels 1,5mm Fixed priority arbiter (line) TDC / counter 100 Mbit/s FIFO SERIALIZER SlowControl 1,5mm 18 mars 2025 Jean.soudier@iphc.cnrs.fr 2
Name FIFO_Data FIFO_Clk FIFO_Full SC_Clk SC_SCK SC_MISO SC_MOSI SC_CSEL TDC_Clk TDC_out Type Digital Output Digital Input Digital Output Digital Input Digital Input Digital Output Digital Input Digital Input Digital Input Digital Output Count (24) 3 1 1 1 1 1 1 1 1 1 Speed 125MHz 125MHz - 40MHz 4MHz 4MHz 4MHz - 250MHz 250MHz/32M Hz - - 500MHz (won t work) 100MHz - PADs count Name PWELL DVDD Type Well Power Count (27) Function 1 2 Digital power Digital ground Analog power Analog ground Substrat DVSS Ground 2 AVDD Power 2 AVSS Ground 2 SUB Substrat 1 RN MAT_RN AB_Clk Digital Input Digital Input Digital Output 1 1 1 PULSE_CMD PIX_BIAS Digital Output Analog Input 1 8 18 mars 2025 Jean.soudier@iphc.cnrs.fr 3
Integration [M1 to M4] : FIFO, Slow control, Column, Pixel [M1 to M3] : Digital In Pixel, Line, VCO, TDC [M1 to M2] : Biasing [ZA] : Name 18 mars 2025 Jean.soudier@iphc.cnrs.fr 4
Integration Row selection [M7] Req, Ack [M1|3] RN, Col, Modes [M4] 18 mars 2025 Jean.soudier@iphc.cnrs.fr 5
Circuit Communications Slow Control over SPI (16bits => 4b CONTROL, 4b SELECTION, 8b DATA) FIFO double entry asynchronous (24b x 64w) 3 Serializer of 8bits (24b/3) TDC counter 13bits for timestamping 18 mars 2025 Jean.soudier@iphc.cnrs.fr 6
Slow control registers (SPI) Address Usage Direction Control (4b) Address (4b) Value (8b) 0 - 7 Column mask selection Row selection W Control Usage 8-9 W 10 TDC, Digital pixel and FIFO tuning Matrix and VCO tuning Fifo information pop R W 2 Set register 11 W 3 Get register 12 4 Reset 13 Fifo information push Test reg 0XF1 R 5 Get SPI data 14 R 6 Get ID 0xABCD 15 Test reg 0xE2 R 18 mars 2025 Jean.soudier@iphc.cnrs.fr 7
Schematic FIFO 24b x 128w Fast OR | Pixels (1b) Timestamp (Gray 13b) Address (10b) FIFO reset is at least 3 clock cycle with RN down 18 mars 2025 Jean.soudier@iphc.cnrs.fr 8
Status Design VCO RTL/Schematic OK Simulation OK Layout OK Post-Simulation To do (Isabelle) Designer Jean Biasing Digital pixel Analog Pixel (integration) Columns Line FIFO & Serializer OK OK - - OK - In progress OK OK To do (Isabelle) OK To do (Andre ) Jean Jean Jean OK OK OK OK OK OK OK OK OK OK OK Hold + RN SM Jean Jean Christophe Slow Control TDC PAD SPARC (Top) OK OK OK OK OK OK OK OK OK OK OK Integration OK OK OK LVS, DRC, IR_DROP, STA Jean Jean Jean Jean 18/03/2025 Jean.soudier@iphc.cnrs.fr
Status Design VCO RTL/Schematic Post-simulation multi-corner, jitter Biasing Digital pixel Analog Pixel (integration) Columns Line FIFO & Serializer Slow Control TDC PAD SPARC (Top) Routing, Post-simulation OK M7 via access, Post-simulation Replace pins OK Hold checks, RN SM, pin, stripes, shape OK OK Separator, Replace Annoter RTL, floorplan, power routing, pre-routing, DRV, STA(glitch), LVS, DRC, IR Drop, Functionnal verifications, perfomances 18/03/2025 Jean.soudier@iphc.cnrs.fr
STA Setup violations on TDC->FIFO & Sel_Reg Setup violations on MAT->FIFO, Hold TDC 18/03/2025 Jean.soudier@iphc.cnrs.fr
Calendar S24: Finish FIFO + Biasing S25-27: Holidays (mail) S28: Finish integration S29: STA/IR Drop S30: LVS/DRC S31: Functionnal 18/03/2025 Jean.soudier@iphc.cnrs.fr
Tanks you for your attention 18/03/2025 Jean.soudier@iphc.cnrs.fr
FIFO floorplan DataIn [23:10] Clk_push, DataIn [0:9] Pop_*, push_* PAD (RN, CLK_POP, push_full, DataOut[2:0], Fifo_clk_pop, push_empty) 18/03/2025 Jean.soudier@iphc.cnrs.fr
