Sequential Networks Implementation Techniques

cse 140 components and design techniques l.w
1 / 27
Embed
Share

Learn about sequential networks implementation techniques including Mealy and Moore machines, excitation table procedures, state tables, logic diagrams, and more in digital systems design.

  • Sequential Networks
  • Implementation Techniques
  • Mealy Machines
  • Moore Machines
  • Digital Systems

Uploaded on | 0 Views


Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.

E N D

Presentation Transcript


  1. CSE 140: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

  2. Implementation Format and Tool Mealy & Moore Machines, Excitation Table Procedure State Table to Logic Diagram Excitation Tables FFs Examples 2

  3. Canonical Form: Mealy and Moore Machines Mealy Machine: yi(t) = fi(X(t), S(t)) Moore Machine: yi(t) = fi(S(t)) si(t+1) = gi(X(t), S(t)) x(t) x(t) y(t) y(t) C1 C2 C1 C2 CLK CLK S(t) S(t) Moore Machine Mealy Machine 3

  4. iClicker In the logic diagram below, a D flip-flop has input x and output y. A: x= Q(t), y=Q(t) B: x=Q(t+1), y=Q(t) C: x=Q(t), y=Q(t+1) D: None of the above y x Q D CLK 4

  5. Understanding Current State and Next State in a sequential circuit Yesterday is gone. Tomorrow has not yet come. We have only today. Let us begin. today Mother Teresa sunrise 5

  6. Implementation Format Canonical Form: Mealy & Moore machines State Table Netlist Tool: Excitation Table x(t) y(t) C1 C2 CLK Q(t) Q(t+1) = g(x(t), Q(t)) Circuit C1 y(t) = f(x(t), Q(t)) Circuit C2 6

  7. Implementation Tool: Excitation Table Example: State Table id x(t) Q(t) Q(t+1) 0 0 0 1 1 1 1 0 2 0 0 1 3 1 1 0 x(t) C1 Q(t) CLK Find D, T, (S R), (J K) to drive F-Fs 7

  8. Implementation Tool: Excitation Table Example: State Table id x(t) Q(t) Q(t+1) 0 0 0 1 1 1 1 0 2 0 1 1 3 1 1 0 Excitation Table x(t) Q(t) id x(t) Q(t) T(t) Q(t+1) T(t) C1 0 0 0 1 1 Q(t) 1 1 1 1 0 CLK 2 0 1 0 1 3 1 1 1 0 Example with T flip flop 8

  9. Implementation Tool: Excitation Table Implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)) Example: Excitation Table x(t) Q(t) id x(t) Q(t) T(t) Q(t+1) C1 Q(t) 0 0 0 1 1 CLK 1 1 1 1 0 2 0 1 0 1 3 1 1 1 0 9

  10. Implementation: Procedure State Table => Excitation Table Problem: To implement C1, we need D(t), T(t), (S(t) R(t)), (J(t) K(t)) as functions of (x,Q(t)). 1. From state table, we have NS: Q(t+1) = g(x(t),Q(t)) 2. Excitation Table of F-Fs: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). 3. Combining 1 and 2, we have excitation table of C1: D(t), T(t), (S(t) R(t)), (J(t) K(t)) = h(x,Q(t)). 10

  11. Implementation: Procedure F-F State Table <=> F-F Excitation Table DTSRJK PS Q(t) T F-F NS Q(t+1) D F-F D(t)= eD(Q(t+1), Q(t)) T(t)= eT(Q(t+1), Q(t)) SR F-F S(t)= eS(Q(t+1), Q(t)) R(t)= eR(Q(t+1), Q(t)) JK F-F J(t)= eJ(Q(t+1), Q(t)) K(t)= eK(Q(t+1), Q(t)) NS Q(t+1) PS DTSRJK Q(t) 11

  12. Excitation Table State table of JK F-F: JK 00 0 1 11 1 0 10 1 1 01 0 0 0 1 Q(t+1) Q(t) Excitation table of JK F-F: Q(t+1) NS PS 0 1 0 1 0- -1 1- -0 Q(t) JK Ex: If Q(t) is 1, and Q(t+1) is 0, then JK needs to be -1. 12

  13. Excitation Tables and State Tables Excitation Tables: PSNS State Tables: 00 0 1 1 Q(t) Q(t+1) JK 10 1 1 01 0 0 11 1 0 JK 1 0 0- -1 0 1- -0 0 1 Q(t+1) Q(t) SR PSSR SR Q(t+1) PSNS 10 1 1 01 0 0 11 - - 00 0 1 1 0 0 1 0 1 10 -0 0- XY Q(t) Q(t) iClicker A.XY= -1 B. XY= 01 C. XY= 10 D.XY= 1- E. None of the above Q(t+1) 13

  14. Excitation Tables and State Tables Excitation Tables: State Tables: T T Q(t+1) PSNS PST 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 Q(t) Q(t) Q(t+1) D D Q(t+1) PSNS PSD 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 Q(t) Q(t) Q(t+1) 14

  15. Implementation: Procedure State table: y(t)= f(Q(t), x(t)), Q(t+1)= g(x(t),Q(t)) Excitation table of F-Fs: D(t)= eD(Q(t+1), Q(t)); T(t)= eT(Q(t+1), Q(t)); (S, R), or (J, K) From 1 & 2, we derive excitation table of the system D(t)= hD(x(t),Q(t))= eD(g(x(t),Q(t)),Q(t)); T(t)= hT(x(t),Q(t))= eT(g(x(t),Q(t)),Q(t)); (S, R) or (J, K). Use K-map to derive combinational logic implementation. D(t)= hD(x(t),Q(t)) T(t)= hT(x(t),Q(t)) y(t)= f(x(t),Q(t)) 1. 2. 3. 4. 15

  16. Implementation: Example Implement a JK F-F with a T F-F J Q Q Q K C1 T Q(t+1) = h(J(t),K(t),Q(t)) = J(t)Q (t)+K (t)Q(t) Implement a JK F-F: JK PSJK 00 0 1 01 0 0 10 1 1 11 1 0 0 1 Q(t) 16

  17. Example: Implement a JK flip-flop using a T flip-flop i.e. Q(t+1)(t) = JQ (t)+K Q(t) Excitation Table of T Flip-Flop Q(t+1) PSNS State table: y(t)= f(Q(t), x(t)), Q(t+1)= g(x(t),Q(t)) Excitation table of F-Fs: D(t)= eD(Q(t+1), Q(t)); T(t)= eT(Q(t+1), Q(t)); (S, R), or (J, K) 3. From 1 & 2, we derive excitation table of the system D(t)= hD(x(t),Q(t))= eD(g(x(t),Q(t)),Q(t)); T(t)= hT(x(t),Q(t))= eT(g(x(t),Q(t)),Q(t)); (S, R) or (J, K). 4. Use K-map to derive combinational logic implementation. D(t)= hD(x(t),Q(t)) T(t)= hT(x(t),Q(t)) y(t)= f(x(t),Q(t)) 1. 0 0 1 1 1 0 0 1 2. Q(t) Excitation Table of the Design J(t) 0 0 0 0 1 1 1 1 K(t) 0 0 1 1 0 0 1 1 Q(t) 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 0 1 1 1 0 T(t) 0 0 0 1 1 0 1 1 id 0 1 2 3 4 5 6 7 T(t) = Q(t) XOR ( J(t)Q (t) + K (t)Q(t)) 17

  18. Example: Implement a JK flip-flop using a T flip-flop T(J,K,Q): K 0 2 6 4 0 0 1 1 T = K(t)Q(t) + J(t)Q (t) 1 3 7 5 0 1 1 0 Q(t) J J Q T Q K 18

  19. iClicker Before state assignment, the relation of its state table and excitation table is A.One to one B.One to many C.Many to one D.Many to many E.None of the above 19

  20. Lets implement our free running 2-bit counter using T-flip flops S0 S1 S3 S2 State Table Next state S1 S2 S3 S0 PS S0 S1 S2 S3 20

  21. Lets implement our free running 2-bit counter using T-flip flops S0 S1 S3 S2 State Table with Assigned Encoding State Table Next Current 01 10 11 00 0 0 0 1 1 0 1 1 S1 S2 S3 S0 S0 S1 S2 S3 21

  22. Lets implement our free running 2-bit counter using T-flip flops Excitation table id Q1(t) 0 Q0(t) 0 T1(t) T0(t) Q1(t+1) 0 Q0(t+1) 1 0 1 0 1 1 0 2 1 0 1 1 3 1 1 0 0 22

  23. Lets implement our free running 2-bit counter using T-flip flops Excitation table id Q1(t) 0 Q0(t) 0 T1(t) 0 T0(t) 1 Q1(t+1) 0 Q0(t+1) 1 0 1 0 1 1 1 1 0 2 1 0 0 1 1 1 3 1 1 1 1 0 0 23

  24. Lets implement our free running 2-bit counter using T-flip flops Excitation table id Q1(t) 0 Q0(t) 0 T1(t) 0 T0(t) 1 Q1(t+1) 0 Q0(t+1) 1 0 1 0 1 1 1 1 0 2 1 0 0 1 1 1 3 1 1 1 1 0 0 T0(t) = T1(t) = Q0(t+1) = T0(t) Q 0(t)+T 0(t)Q0(t) Q1(t+1) = T1(t) Q 1(t)+T 1(t)Q1(t) 24

  25. Lets implement our free running 2-bit counter using T-flip flops Excitation table id Q1(t) 0 Q0(t) 0 T1(t) 0 T0(t) 1 Q1(t+1) 0 Q0(t+1) 1 0 1 0 1 1 1 1 0 2 1 0 0 1 1 1 3 1 1 1 1 0 0 T0(t) = 1 T1(t) = Q0(t) 25

  26. Free running counter with T flip flops Q0 1 Q T Q Q Q1 T Q T1 T0(t) = 1 T1(t) = Q0(t) 26

  27. Summary: Implementation Set up canonical form Mealy or Moore machine Identify the next states state diagram state table state assignment Derive excitation table Inputs of flip flops Design the combinational logic don t care set utilization 27

Related


More Related Content