Performance Optimization Techniques in Hardware Design

lecture 19 performance optimization n.w
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Learn about performance optimization strategies in hardware design, including pipelining, module partitioning, and useful Verilog features. Explore topics such as 32-bit arithmetic shift right design and horizontal partitioning for efficient circuit implementation.

  • Hardware Design
  • Optimization Techniques
  • Performance
  • Pipelining
  • Verilog

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  1. Lecture 19 Performance Optimization Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/

  2. Project FAQ Correction typo in optical flow: Iy(i, j) = I1(i, j+1) I1(i, j-1) I1(i, j+1) might not exist Mid-project report behavioral Verilog code and testbench show proof of working functional simulation ensure synthesizable codes Use of external memory instantiate in the test bench used for large data array or buffers 2

  3. Arrays, Vectors, and Memories 3

  4. Useful Verilog Features Display tasks $display, $displayb (h, o) in binary, hex, and octal $write, $strobe, $monitor File I/O tasks $fopen, $fclose $fdisplay, $fwrite, $fstrobe, $fmonitor $readmemb, $readmemh: read a text file into memory 4

  5. Module Partitioning Where possible, register module outputs and keep critical path in one block Design Registering pipelining restructure a long data path with several levels of logic and break it up over multiple cycles 5

  6. Pipelining 6

  7. Pipelining 7

  8. Adding Structure Control the structure by using separate assignment and parentheses Example 32-bit arithmetic shift right design 1 design 2 8

  9. 32-Bit Arithmetic Shift Right Design 3 9

  10. 32-Bit Arithmetic Shift Right Optimal structured design 10

  11. 32-Bit Arithmetic Shift Right Without specifying the mux instantiations 11

  12. Horizontal Partitioning Break circuit into horizontal slices to minimize maximum fan-in Example carry lookahead adder: 32-bit adder broken to eight 4-bit blocks 32-bit priority encoder 12

  13. 32-Bit Priority Encoder Restructured with four 8-bit blocks 13

  14. Priority-Encoded Logic vs Balanced Logic If-Then-Else vs Case Statement redundant priority 14

  15. Hierarchy Collapse hierarchy (flattening) more efficient synthesis Add Hierarchy benefit results from structure preservation example: 32-bit decoder least-efficient implementation 15

  16. 32-Bit Decoder More concise representation A balanced tree decoder is even better 16

  17. 32-Bit Balanced-Tree Decoder 17

  18. Performing Operations in Parallel Example linear search 18

  19. Performing Operations in Parallel Example binary search 19

  20. Performing Operations in Parallel Example parallel search 20

  21. MUX for Conditional Assignment Example: counter 21

  22. MUX for Conditional Assignment Example: counter 22

  23. Replication Large fanout manual register duplication to reduce congestion 23

  24. Resource Sharing Optimize area but hurt speed with resource sharing 24

  25. Resource Sharing Optimize area but hurt speed without resource sharing 25

  26. Questions? Comments? Discussion? 26

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