FPGA Implementation of Sobel and Canny Filters
"Learn about the FPGA implementation of Sobel and Canny filters, ideal for fast and efficient edge detection in robotics. Explore the order of operations, test plan, hardware requirements, and approximations used in the process."
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Presentation Transcript
Implementation of Sobel and Canny filters on FPGA By Konstantin Martynov and Angel Carvajal 1
Motivation For Using FPGA Motivation For Using FPGA Mostly robots orient around by finding edges created by objects to find or to avoid those objects. Edge detection done by convolution very expensive operation in software. FPGA could be installed on a robot to make fast, low power, low latency edge detection with maximum speed. 2
Order Of Operations Order Of Operations Convert To Grayscale Apply Sobel Filter Apply Canny Filter 3
Test Plan Test Plan The same function with the same approximations discussed further implemented in matlab and FPGA output should give exactly the same answer. However, To compare effect of approximations correlation coefficient may be used : 4
Sobel Sobel Filter : Gradient Field Filter : Gradient Field Goal: Enhance Edges by creating gradient field. Gradient is calculated by convolution: ??= ? ?? ??= ? ?? Caution! Even though image has 8 bit unsigned pixels, ?? and ?? should be considered as at least 11 bit signed values! Example. For pixel (i, j) of image I : ??, ?,? + ??+1,?+1 ??+1,? 1 + ??,?+1 ??,? 1 = ?? 1,?+1 ?? 1,? 1 1 Hardware Required:Adders, Shifters 5
Sobel Sobel Filter : Extracting Magnitude and Direction Filter : Extracting Magnitude and Direction Goal: Calculate Values needed by Canny Filter Usually magnitude and angle are calculated as follows: 2+ ?? 2 ? = ?? ? = ????2(??,??) However, square root and arctangent are very expensive in hardware, especially since they need to be done for many pixels simultaneously. Approximation for magnitude : ? ??+ ?? 6
Sobel Sobel Filter : Approximation For Direction Filter : Approximation For Direction Only 4 directions possible 2 bits for angle Ideal solution : ? 22.5,22.5 ?? 157.5,202.5 0 ? 22.5,67.5 ?? 202.5,247.5 1 ???. Approximated solution: ??? 5?? ??? 2?? 0 ??? 2?? ??? 5?? 2 ???? ?? ??? ?? ??? ???? ???? 1 ?? ??? ?? ??? ???????? ???? 3 Hardware required : Multipliers, Comparators. 7
Canny Filter: Narrowing Lines Canny Filter: Narrowing Lines Goal: Make width of Edge equal to 1 pixel Gradient Direction is perpendicular to the edge to narrow line need to compare pixel with its neighbors along gradient. If its value is bigger than neighbors and threshold, then make it 255, otherwise 0. To keep track of lines there are 2 different threshold values - ???? ??? ? ?? 8
High Level Design High Level Design FPGA Input Image Grayscale Image From Host (.bin) SceMi DRAM Filtered Image 64 Main Program Cycle Count Filtered Image To Host (.txt) 512 Sobel Filter 10*W 8*W Canny Filter 9
Microarchitecture: Microarchitecture: Sobel Sobel Filter Filter 3*(W+2)*8 W*8 *Gx r1 Wx8 inVector outVector Magnitude r2 Angle 3*(W+2)*8 r3 *Gy W*2 N_loads, Reg_filled inFIFO outFIFO inVector - Vector#(w, Bit#(8)) outVector -Vector#(w, Bit#(10)) r1-r3 Reg#(W+2) N_loads Int#(16) Reg_filled Bool#() r1<- r2; r2<- r3; Reg_filled ? Interface : Sobel Filter HxW 10
Microarchitecture: Canny Filter Microarchitecture: Canny Filter R1, R2, R3 Size(W+2) Cannyin = Vector#(w, Int#(10)) Cannyout = Vector#(w, Int#(8)) N_loads Int#(16) Reg_filled Bool#() Interface: Canny Filter Height (H) Width (W) Threshold (T) Wx8 Cannyout 3*(W+2)x8 R1 R2 Wx8 Cannyin Non-Max Suppression R3 Wx8 N_loads, Reg_filled Wx2 outFIFO inputFIFO R1<- R2; R2<- R3; Reg_filled ? 11
Results : Easy implementation Results : Easy implementation 12
Improved Microarchitecture Improved Microarchitecture Changes : Use 64 byte inputs instead of W byte inputs. Reduces amount of Hardware dramatically Use FIFO inside of interface. This separates registers change from computations 512 *Gx r1 1584 512 inVector outVector Magnitude r2 Angle r3 128 *Gy r2sFIFO Row_count, col_count inFIFO outFIFO inVector - Vector#(64, Bit#(8)) outVector -Vector#(64, Bit#(10)) r1-r3 Reg#(W+2) Row_count bit#(16) Col_count Bit#(16) r1<- r2; r2<- r3; Interface : Sobel Filter HxW 13
Improved Microarchitecture : Registers Improved Microarchitecture : Registers 64 pix 1 pix - Available Data - Data being converted If number of columns ? = ?/64, then N+1 cycles needed to receive and forward whole line. 14
Results : Improved implementation Results : Improved implementation 15
Future Work Future Work 1. Implement Canny filter that uses both lower and higher threshold to keep track of continuous edges. 2. If non compressed data used, output could be as stream of coordinates with nonzero pixel. This is efficient, because after canny filter there is very small fraction of white pixels. 3. Image compression on FPGA to take input and output image formats. 4. Video compression on FPGA to convert video formats. 5. Implement corner detection 16
