Cooperative Cache Scrubbing for Efficient Memory Management in Multicore Systems
Cooperative Cache Scrubbing optimizes memory management in multicore systems by efficiently handling short-lived application objects and reducing unnecessary data writes to memory. By communicating semantic information to hardware caches, dead lines are scrubbed, dirty bits unset, and unnecessary fetches avoided, resulting in better cache utilization and energy savings. Through techniques like generational garbage collection and zero initialization, this approach addresses challenges such as allocation walls, bandwidth, and power limitations, improving system performance and resource utilization.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
E N D
Presentation Transcript
Cooperative Cache Scrubbing Jennifer B. Sartor, Wim Heirman, Steve Blackburn*, Lieven Eeckhout, Kathryn S. McKinley^ PACT 2014 * ^
Multicore Challenge Application Objects rapidly allocated and short-lived Managed language runtime environment Operating System P $ P $ P $ P $ Chip LLC memory (DRAM) p. 2
Problem: Allocation Wall Application Objects rapidly allocated and short-lived Managed language runtime environment Operating System P $ P $ P $ P $ Chip DEAD DEAD DEAD LLC DEAD DEAD DEAD memory (DRAM) p. 3
Problem: Bandwidth & Power Wall Application Objects rapidly allocated and short-lived Managed language runtime environment Operating System Zero initialization P $ P $ P $ P $ Chip DEAD DEAD DEAD 0000000 LLC DEAD DEAD 0000000 DEAD memory (DRAM) p. 4
Cooperative Cache Scrubbing Application Objects rapidly allocated and short-lived Managed language runtime environment Operating System Zero initialization P $ P $ P $ P $ Chip DEAD DEAD 0000000 0000000 LLC LLC DEAD DEAD DEAD DEAD memory (DRAM) p. 5
Generational Garbage Collection Mature Nursery Young objects die quickly Nursery Traced for live objects Copy to mature space Reclaimed en masse DEAD DEAD DEAD DEAD LLC DEAD DEAD 8MB p. 6
Dead Data Written Back? Application Managed language runtime environment Operating System P $ P $ P $ P $ Chip DEAD DEAD DEAD LLC DEAD DEAD DEAD memory (DRAM) p. 8
Cooperative Cache Scrubbing Communicate managed language s semantic information to hardware Caches Scrub dead lines Invalidate Unset dirty bit Zero lines without fetch Result Better cache management Avoid traffic to DRAM Save DRAM energy writes reads p. 10
Dead Data Written in Cache? Mature Nursery Young objects die quickly Nursery Traced for live objects Copy to mature space Reclaimed en masse DEAD DEAD 0000000 DEAD LLC DEAD DEAD DEAD DEAD DEAD p. 11
SW-HW Cooperative Scrubbing Software Identify cache line-aligned dead/zero region Generational Immix collector (stop-the-world) After nursery collection, call scrub instruction on each line in entire range Call zero instructions to zero region (32KB) Hardware p. 13
SW-HW Cooperative Scrubbing Software Hardware Scrubbing (LLC) clinvalidate: invalidates cache line clundirty: clears dirty bit clclean: clears dirty bit, moves line to LRU Zeroing (L2) clzero: zero cache line without fetch Modifications to MESI cache coherence protocol Back-propagation from LLC to L1/L2 cache levels Local coherence transitions (no off-chip) PowerPC s dcbi, ARM PowerPC s dcbz p. 14
MESI Coherence Transitions M E clclean/- clclean/- clinvalidate/- clinvalidate/- clclean/- clclean/- I S clinvalidate/- p. 15
MESI Coherence Transitions clzero/- M E clzero/- clzero/BusInvalidate BusInvalidate external: from another LLC I S BusInvalidate p. 16
Methodology Sniper simulator 4 cores, 8MB shared L3 (LLC), McPAT Extensions for JVM Works with JIT compiler Emulate system calls (futex & nanosleep) JVM-simulator communication with new instruction Jikes RVM 3.1.2 and DaCapo benchmarks Generational Immix garbage collector 4 application, 4 GC threads 2x minimum heap Replay compilation, 2ndinvocation p. 17
DRAM Writes (8MB nursery) 120 100 Writes/Baseline (%) 80 clinvalidate clundirty clclean clzero clclean+clzero 60 40 20 0 p. 18
DRAM Writes (8MB nursery) 120 100 Writes/Baseline (%) 80 clinvalidate clundirty clclean clzero clclean+clzero 60 40 20 0 p. 19
DRAM Writes (8MB nursery) 120 100 Writes/Baseline (%) 80 clinvalidate clundirty clclean clzero clclean+clzero 60 40 20 0 p. 20
DRAM Reads (8MB nursery) 225 200 Reads/Baseline (%) 175 150 125 clinvalidate clundirty clclean clzero clclean+clzero 100 75 50 25 0 p. 21
DRAM Reads (8MB nursery) 225 200 Reads/Baseline (%) 175 150 125 clinvalidate clundirty clclean clzero clclean+clzero 100 75 50 25 0 p. 22
DRAM Reads (8MB nursery) 225 200 Reads/Baseline (%) 175 150 125 clinvalidate clundirty clclean clzero clclean+clzero 100 75 50 25 0 p. 23
DRAM Reads (8MB nursery) 225 200 Reads/Baseline (%) 175 150 125 clinvalidate clundirty clclean clzero clclean+clzero 100 75 50 25 0 p. 24
DRAM Reads (8MB nursery) 225 200 Reads/Baseline (%) 175 150 125 clinvalidate clundirty clclean clzero clclean+clzero 100 75 50 25 0 p. 25
Dynamic DRAM Energy (8MB nursery) 80 70 Energy Reduction (%) 60 50 clinvalidate clundirty clclean clzero clclean+clzero 40 30 20 10 0 Mean p. 26
Dynamic DRAM Energy (8MB nursery) 80 70 Energy Reduction (%) 60 50 clinvalidate clundirty clclean clzero clclean+clzero 40 30 20 10 0 Mean p. 27
Total DRAM Energy 25 20 Energy Reduction (%) 15 clinvalidate clundirty clclean clzero clclean+clzero 10 5 0 4M 8M 16M -22% -5 p. 28
Total DRAM Energy 25 20 Energy Reduction (%) 15 clinvalidate clundirty clclean clzero clclean+clzero 10 5 0 4M 8M 16M -22% -5 p. 29
Total DRAM Traffic 100 75 Traffic Reduction (%) 50 clinvalidate clundirty clclean clzero clclean+clzero 25 0 4M 8M 16M -25 -14x -50 p. 30
clclean+clzero Improvements 100% 90% 80% 70% 60% 50% 40% 4MB 8MB 16MB 30% 20% 10% 0% p. 31
Related Work Cooperative cache management ESKIMO by Isen & John, Micro 09 Useless reads and writes to DRAM by sequential C programs Reduce energy Require large map in hardware, extra cache bits Wang et al., PACT 02/ ISCA 03; Sartor et al., 05 C & Fortran static analysis to give cache hints to evict or keep data Zero initialization [Yang et al., OOPSLA 11] Studied costs in time, cache and traffic Use non-temporal writes to DRAM, increase bandwidth p. 32
Conclusions Software-hardware cooperative cache scrubbing Leverages region allocation semantics Changes to MESI coherence protocol New multicore architectural simulation methodology Reductions 59% traffic 14% DRAM energy 4.6% execution time DEAD 0000000 http://users.elis.ugent.be/~jsartor/ p. 33
Execution Time (8MB nursery) 7 Execution Time Reduction (%) 6 5 clinvalidate clundirty clclean clzero clclean+clzero 4 3 2 1 0 Mean p. 35
Changes to MESI coherence protocol State clinvalidate clundirty/clcl ean invalidate L1/L2 (no WB) E (clclean LRU) invalidate L1/L2 (clclean LRU) invalidate L1/L2 (clclean LRU) clzero BusInvalidate M invalidate L1/L2 (no WB) I invalidate L1/L2 (no WB) I E invalidate L1/L2 I invalidate L1/L2 I M invalidate L1/L2 I invalidate L1/L2 I S BusInvalidate M I BusInvalidate M p. 36
Total DRAM Energy (8MB nursery) 60 50 Energy Reduction (%) 40 clinvalidate clundirty clclean clzero clclean+clzero 30 20 10 0 -10 p. 37
Execution Time p. 39
