AM263x MCU I/O Failsafe and Over-Voltage Operations

AM263x Over-Voltage and Failsafe I/O Operations 1

Summary This presentation is a discussion of the AM263x MCU analog input and digital I/O as they pertain to failsafe and over-voltage operation. This is intended as an introduction into the current I/O implementation, and PCB mitigation strategies necessary for operating the AM263x in a higher-voltage environment where I/O will be exposed to voltages prior to device power on and voltages exceed Vmax during normal operation. Outline Baseline Device I/O Architecture Powered-off failsafe mitigation strategies Powered-on/off over-voltage mitigation strategies Design Optimization Trades Future Development 2

AM263X DEVICE I/O ARCHITECTURE 3

AM263x Device I/O Digital I/O The AM263x MCU is a 45-nm CMOS device optimized for power/thermal sensitive digital processing and lower voltage digital and analog I/O operation All AM263x analog input and digital I/O have the same basic over-voltage/ESD structures LVCMOS process optimized for 3.3V operation with fast reacting ESD current directing diode structures ESD diodes sized for high current, low-on-time, operation assuming HBM, CMB transient over- voltage protection between VSS-0.3V and VDD+0.3V No power-on, or power-off, fail-safe structures design into these I/O. VDDS33 Core Logic RX TX VSS Analog Input VDDA33 Core Logic SAR ADC VSS See the AM263x Sitara and absolute maximum conditions Microcontrollers datasheet (Rev. C) for recommended 4

AM263x Device I/O - Failsafe Analog Input Powered-Off Failsafe Operation Limitations With these I/O in a powered-off state, voltages presented to the pad can conduct and start to power the digital/analog power rails through leakage pathways. This could result in unwanted digital I/O state changes on connected devices. Therefore, additional external circuitry is required to prevent these leakage paths from becoming charged. VDDA33 Other Logic R.leakage Core Logic SAR ADC + Vinput VSS VSS Analog Input VDDA33 Other Logic R.leakage Core Logic SAR ADC Failsafe Circuit + Vinput VSS VSS VSS 5

AM263x Device I/O - Overvoltage Analog Input Powered-On/Off Over-Voltage Operation Limits Input voltages beyond the absolute maximum operating condition ranges of VDDS33 + 0.3 and VSS 0.3V will cause the ESD diodes to start conducting. If these diodes conduct at high duty cycle and without current limit, the diodes will be damaged. Additional signal integrity on interfaces cannot be guaranteed in over-voltage conditions (diodes conducting) Therefore, additional external circuitry is required to prevent these I/O pads from seeing constant duty, over-voltage conditions with unlimited current. VDDA33 Core Logic SAR ADC + Vinput VSS VSS Analog Input VDDA33 Over-Voltage Circuit Core Logic SAR ADC + Vinput VSS VSS VSS 6

POWERED-OFF FAILSAFE MITIGATION 7

AM263x Powered-off Over-Voltage/Failsafe Mitigation In the powered-off state, TI recommends that the I/O pads are shorted to VSS through an external shunt circuit to prevent any PAD voltage developing. This mitigates the failsafe condition as well as any over-voltage condition in the powered-off state. . Switch should be sized for minimum cost/floorplan area Gate must be compatible with available control logic prior to AM263x power-on Circuit here relies on a generic BSS123 NMOS FET and current limiting resistor with 170mA Ids (continuous) limit Analog Input VDDA33 Rlimit Core Logic SAR ADC >95ohm + V.input <16V BSS123 NFET Vfailsafe Enable <20V + VSS VSS For best signal integrity, recommend separate shunt for each failsafe I/O Shunt FET pad be placed in-line with functional traces such that no additional stubs are formed 8

POWERED-ON/OFF OVER-VOLTAGE MITIGATION 9

AM263x Powered-On/Off Over-Voltage (Failsafe Mitigation) In the case of driving a SAR ADC, these failsafe shunt elements will likely be combined with the necessary driver op-amp and input filter matched to the SAR ADC sampling rate and parasitics Analog Input VDDA33 TLV9161-Q1 VDDA33 R.limit V.mcu <VDDA33 R.filter + Core Logic SAR ADC V+ V.input <16V + V C.filter R.fb1 VSS High-voltage/failsafe compatible op-amp like the TLV91x can be utilized as an over-voltage clamp. External failsafe in this case would not be needed since the VDDA33 rail would be powered off and all input would be shunted through the larger ESD/over- voltage structures of the attached op- amp R.fb2 See reference [1] 10

AM263x Powered-On/Off Over-Voltage (Failsafe Mitigation) If an ADC is connected to a non-failsafe driving op-amp, then an additional circuit on the op-amp input is required for separate failsafe/over- voltage protection for the op-amp itself Analog Input VDDA33 Non-Failsafe Op-Amp R.limit > (V.input / Ids ) V.mcu <VDDA33 VDDA33 R.filter + Core Logic SAR ADC V+ >94ohm + V.input <16V V BSS123 NFET C.filter R.fb1 Vfailsafe Enable <20V + VSS R.fb2 VSS If an ADC pad is disconnected from a driving op-amp, then additional circuit is required for separate failsafe/over-voltage protection for the MCU pad. R.filter could also serve as current limiting element. Analog Input VDDA33 Non-Failsafe Op-Amp R.limit > (V.input / Ids ) VDDA33 R.filter/R.limit + Core Logic SAR ADC V+ >94ohm + V.input <16V V BSS123 NFET C.filter R.fb1 + Vfailsafe Enable <20V + VSS R.fb2 VSS VSS This likely represents a super-set of external circuitry necessary on the ADC pads 11

AM263x Powered-On/Off Over-Voltage Mitigation In the case of a digital I/O, two over- voltage solutions are recommended 1) Current limiting resistor: MCU voltage clamped by ESD diodes running over-voltage, but at reduced input current (< 2mA) 2) Digital level-shifter (discrete or IC): MCU operating within normal datasheet limitations (with/without failsafe) Digital I/O VDDA33 R.limit > (V.input / Ids ) Core Logic RX BSS123 NFET 8kohm + TX V.input <16V + Vfailsafe Disabled VSS VSS VHIGH <16V Digital I/O VDDS33 VDDS33 10kohm 10kohm V.mcu <VDDS33 Core Logic RX Simple current limiting resistor is cost- optimal, but comes with potential for signal integrity, timing and full POH entitlement validation effort + BSS123 NFET TX V.input <16V VSS 12

AM263x Powered-On/Off Over-Voltage Mitigation Level translator IC (like CD401B-Q1 uni-directional) are high voltage and failsafe tolerant. This lets the MCU operate within normal datasheet parameters VDDS33 Digital I/O VHIGH <16V VDDS33 V.mcu <VDDS33 RX RX RX RX V.input <16V CD401B-Q1 Level Translator V.input <16V V.input <16V V.input <16V 13

DESIGN OPTIMIZATION TRADES 14

AM263x Over-Voltage and Failsafe Tradeoffs TI MCU designs have traditionally attempted to optimize for die/package cost, power, and thermal design of our devices at a given MCU/DSP operating point Watts/USD Die-Area/USD Drystone/USD TI MCU design is tailored for an individual sub-system optimization approach where individual system blocks should be optimized for their intended purpose Although a disadvantage in some high-voltage compatibility cases, utilizing faster, cost-optimal I/O with the same process as our core logic, leaves the system designer maximum flexibility to add capability/cost to their system only where necessary This is in contrast to an approach where all I/O may be natively compatible in the most extreme conditions, but where all systems pay the maximum cost for this capability, even when it is not needed. 15

AM263x Over-Voltage and Failsafe Tradeoffs MCU Failsafe Over-Voltage Core Performance Peripheral Performance Native (maximized/USD) Digital Process External External Native (maximized/USD) High-Voltage Process Native Native Unoptimized (limited/USD) Unoptimized (limited/USD) 16

AM263x Over-Voltage and Failsafe Tradeoffs Parameter AM263x MCU Cost Failsafe Components Cost - Discrete High-Voltage + Failsafe Components Cost - Discrete IC failsafe/high-voltage - digital (4-bits) Value Units Notes 8.32 USD $0.01 USD $0.01 USD $0.15 USD See actual 1ku pricing AM2634CODFHAZCZR example See BSS13 NMOS 1ku pricing for example See BSS13 NMOS 1ku pricing for example See CD401B-Q1 1ku pricing for example, scales better with more I/O Number I/O Failsafe I/O High-Voltage I/O 4 4 just as an example just as an example Discrete External Cost/Failsafe I/O Cost/High-Voltage and Failsafe I/O $0.05 $0.05 IC External Cost/High-Voltage I/O $0.15 Total MCU integration (other items unaccounted for) Discrete IC $8.37 $8.47 17

FUTURE DEVELOPMENT 18

AM263x Future Development For the near-term, recommend new over-voltage and failsafe designs utilize external circuitry to supplement AM263x I/O TI requires additional device characterization to validate I/O in over-voltage and failsafe status Must ensure full POH entitlement in these states Minimum of 6 months of additional physical validation work required to qualify this mode of operation No additional validation work started on this yet TI also strongly considering the inclusion of minimal numbers of high-voltage and failsafe I/O in future devices This must be balanced against the overall die area cost across TI MCU use- cases Only the earliest of design discussions have begun on this topic No device roadmap specifications yet 19

References 1. Circuit for driving a switched-capacitor SAR ADC with a buffered instrumentation amplifier: https://www.ti.com/lit/an/sbaa277a/sbaa277a.pdf 2. High-Voltage Signal Conditioning for Low-Voltage ADCs https://www.ti.com/lit/an/sboa097b/sboa097b.pdf 3. Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs https://www.ti.com/lit/an/sboa307/sboa307.pdf 20